a verilog syntax issue that i can't figure out

Hello

Looks like you are running the FIFO version of the controller?

That module is not actual meant to be compiled, its an example how you should instantiate the design it in to you own top module in your design.

either past it in or do a 'include on you top module and all you need to do is to add the pin out and you are ready to go.

I haven't tried the FIFO module very much so please be kind to report any problem.

The FIFO module has no documentation, check the SW/main.c for clues how to interface with it.

/Adam