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Honored Contributor
Honored Contributora verilog syntax issue that i can't figure out
i have a verilog design of an sdcontroller which i obtained from opencores and which iam trying to simulate. well its a certified design but its giving one peculiar error. one of the design files whe...
Altera_ForumHonored Contributor
Honored ContributorHello
Looks like you are running the FIFO version of the controller? That module is not actual meant to be compiled, its an example how you should instantiate the design it in to you own top module in your design. either past it in or do a 'include on you top module and all you need to do is to add the pin out and you are ready to go. I haven't tried the FIFO module very much so please be kind to report any problem. The FIFO module has no documentation, check the SW/main.c for clues how to interface with it. /Adam
