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Altera_Forum's avatar
Altera_Forum
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14 years ago

A question about fitting resource usage summary

I have synthesis an Opencore to FPGA DE0 board, and I see the fitting resource usage summary in the compilation report which shows as below

Total logic elements 2,039 / 15,408 ( 13 % )

Combinational with no register 1343

register only 35

Combinational with a register 661

Logic element usage by number of LUT inputs

-- 4 input functions 1279

-- 3 input functions 478

-- <=2 input functions 247

register only 35

Logic elements by mode

normal mode 1824

arithmetic mode 180

But when I reduced a JNE instrucion from the opencore ,and synthesis again, it shows

Total logic elements 2,044 / 15,408 ( 13 % )

Combinational with no register 1348

register only 37

Combinational with a register 659

Logic element usage by number of LUT inputs

-- 4 input functions 1281

-- 3 input functions 482

-- <=2 input functions 244

register only 37

Logic elements by mode

normal mode 1827

arithmetic mode 180

It seems the logical elements it used increased? Why? Another question is in theory, when I reduced the instructions, the power consumption of the FPGA core should reduced, right? And is there any theory can explain the change of power consumption from this usage report? Thank you very much

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thank you for reply. the opencore is open MSP430 core, then I reduced the JNE instruction from the openMSP430 core, and synthesis it again

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I'm not familiar with the core, but having written a microprocessor core (the Open8 uRISC), I can tell you that it isn't uncommon to see the compiler do surprising things in the face of "optimization"

    I've written fairly simple address decoders in two styles. For some modules, I get lower usage with one style and not the other; and yet for other modules the reverse is true.

    I am assuming from the mnemonic that JNE is Jump if Not Equal. I would imagine the ALU already creates the logic for equality testing, and the JNE instruction simply examines the status of the flag (probably the Z flag). This would explain the almost infinitesimal change in resource usage. The fact that it slightly increased may also come down to resource sharing that has changed as well.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Hi Jshmalet

    Thanks very much for Open8_urisc core in opencores.org.

    1. I find all the individual files including CPU; ALU,GPIO, CLK_DETECT etc but I don't find a top level VHDL file that binds it together.

    2. Because it is written in VHDL'93 syntax and I am using ISE 10.1 (may be that uses VHDL 87) which uses different component declaration in o8_ram_1K which I tried to change by declaring a separate component (ram_1K_core) and a call to the component as in old style VHDL but it still din't like it complaining generic Address is not given value....

    If you can please provide the top level file or any instructions that how can i put them together; I would really appreciate and if it can be a quick response that would be a real bonus.....

    Also any help in sorting the U_RAM and U_ROM_CORE(o8_ram_1K).... Looking forward to your help
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    It would appear ram_1k_core is missing from the repo.

    You will have to contact the author to find the missing files.

    This is '93 syntax for direct instantiation. ISE should support it. But the core is missing, hence why it wont compile.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Thanks Tricky; The email address of the authors donot work.....Jshmalet is the author and hence I am trying to approach him. Also the top level module is missing

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    --- Quote Start ---

    Thanks Tricky; The email address of the authors donot work.....Jshmalet is the author and hence I am trying to approach him. Also the top level module is missing

    --- Quote End ---

    Generally I never trust anything from OpenCores.

    I have found stuff to lack documentation, have poor coding styles and as you have found, missing modules.

    If you need support you are reliant on the original author, who may not have worked on it for a long time, or not be interested.

    Generally, use at your own peril.
  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    Yes, I understand. Cheers Tricky. I don't understand why the contact email addresses are not the right ones. Emails get bounced

  • Altera_Forum's avatar
    Altera_Forum
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    8 years ago

    The most recent files seem to be from nearly 2 years ago

    People'e email addresses change, people move on...

    showing just how untrustworthy opencores can be.