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Altera_Forum's avatar
Altera_Forum
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14 years ago

A question about fitting resource usage summary

I have synthesis an Opencore to FPGA DE0 board, and I see the fitting resource usage summary in the compilation report which shows as below Total logic elements 2,039 / 15,408 ( 13 % ) Combinat...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Hi Jshmalet

Thanks very much for Open8_urisc core in opencores.org.

1. I find all the individual files including CPU; ALU,GPIO, CLK_DETECT etc but I don't find a top level VHDL file that binds it together.

2. Because it is written in VHDL'93 syntax and I am using ISE 10.1 (may be that uses VHDL 87) which uses different component declaration in o8_ram_1K which I tried to change by declaring a separate component (ram_1K_core) and a call to the component as in old style VHDL but it still din't like it complaining generic Address is not given value....

If you can please provide the top level file or any instructions that how can i put them together; I would really appreciate and if it can be a quick response that would be a real bonus.....

Also any help in sorting the U_RAM and U_ROM_CORE(o8_ram_1K).... Looking forward to your help