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Honored Contributor
Honored ContributorA problem with using DCFIFO (lpm_fifo)
Hello!
In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect the wrfull signal go high on a 4th write I am surprised when the wrfull goes high right after the first write cycle. I have tried to enable all the protection circuits available in this component but still not get the good results. The fifo component is on the data input to the uart transmitter... At this point I would appreciate a fresh pair of eyes look from somebody on the forum - maybe there is something obvious wrong and I do not see it. Can you help me? Here is the fragment of the circuit with the fifo component: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=fifo.jpg And here simulation with the wrfull signal going high after first write: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=simul.jpg Please note, wrfull signal is visible in the simulation as TX_EMPTY and is inversed. Any ideas where and what to check? Thanks!12 Replies
Altera_ForumHello,
You can provide a running rdclk also and check the behavior and do a clear at the start of simulation. As there is no rdclk (and not reset), may be that the rdptr is stuck at some value? Eldos- Altera_Forum
I have enabled wrempty and wrusedw[] outputs in the fifo component and simulated again.
The wrempty goes low right after positive edge of the wrclk when wrreq is high. This is OK. Then wrreq ends before the next positive edge of the wrclk. This is OK. The wrusedw[] goes to value 1 right after next positive edge of the wrclk. This is still OK. Then after next positive edge of the wrclk wrfull goes to high (and inversed signal called TX_EMPTY goes low). This is NOT EXPECTED. My wrreq signal lasts 1.5 wrclk and starts after the positive edge and ends after the negatie edge on the simulator. Here is the snapshot of the simulator: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=simul2.jpg I have also made another experiment, and extended the wrreq signal to last 3 wrclks. The wrfull also changed the same time, one clock after wrusedw[] changed from 0 to 1. Here is a picture from the simulator: http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view¤t=simul3.jpg Why is wrfull asserted if the fio is not full??? Something is seriously wrong here...
