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Altera_Forum
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16 years ago

A problem with using DCFIFO (lpm_fifo)

Hello! In my design I have a 8bit x 4 words dual-clock fifo component (LPM_FIFO+) and I observe a very strange behaviour or the wrfull output signal. Since I have fifo 4 word-deep I expect...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hello,

You can provide a running rdclk also and check the behavior and do a clear at the start of simulation.

As there is no rdclk (and not reset), may be that the rdptr is stuck at some value?

Eldos