A problem with using DCFIFO (lpm_fifo)

I have enabled wrempty and wrusedw[] outputs in the fifo component and simulated again.

The wrempty goes low right after positive edge of the wrclk when wrreq is high. This is OK.

Then wrreq ends before the next positive edge of the wrclk. This is OK.

The wrusedw[] goes to value 1 right after next positive edge of the wrclk. This is still OK.

Then after next positive edge of the wrclk wrfull goes to high (and inversed signal called TX_EMPTY goes low). This is NOT EXPECTED.

My wrreq signal lasts 1.5 wrclk and starts after the positive edge and ends after the negatie edge on the simulator.

Here is the snapshot of the simulator:

http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view&current=simul2.jpg

I have also made another experiment, and extended the wrreq signal to last 3 wrclks.

The wrfull also changed the same time, one clock after wrusedw[] changed from 0 to 1.

Here is a picture from the simulator:

http://s820.photobucket.com/albums/zz128/pszemol_alt/?action=view&current=simul3.jpg

Why is wrfull asserted if the fio is not full??? Something is seriously wrong here...