Hmm, I got the following silly example working on DE2-70, but haven't yet written a more robust memory control, assigned timing constraints, used a PLL, or used the burst mode. Also, I don't have the Cyclone III kit, so it'll likely take some adoption to get it running.
The example waits for a char c over the serial port and it, as well as c+1 and c+2 in a buffer, then proceeds to replay the whole buffer. The char '0' resets the buffer.
Unlike what I suggested and what is recommended everywhere, using an inverted clock didn't work well for me. The essence is this (WARNING, this isn't production quality code,
just a quick example):
assign oSRAM_CLK = iCLK_50;
assign oSRAM_ADSP_N = 1; // We use ADSC#
assign oSRAM_BE_N =~0; // byte write enable
assign oSRAM_CE1_N = 0; // chip enable
assign oSRAM_CE2 = 1; // chip enable
assign oSRAM_CE3_N = 0; // chip enable
reg SRAM_D_ena = 0;
reg SRAM_DPA_out = 0;
reg SRAM_D = 0;
assign SRAM_DPA = SRAM_D_ena ? SRAM_DPA_out : 4'hZ;
assign SRAM_DQ = SRAM_D_ena ? SRAM_D : 32'hZ;
/* Demo state machine: When we get a serial char, we add it to the buffer
and prints the whole buffer again */
reg state = 0;
reg wp = 0;
reg rp = 0;
always @(posedge iCLK_50) begin
// Set up default values so that writes below are one-shot
oSRAM_ADSC_N <= 1;
oSRAM_GW_N <= 1;
oSRAM_ADV_N <= 1;
oLEDR <= state;
case (state)
0: begin // wait for input
oSRAM_OE_N <= 1; // close the SSRAM DQ drivers
SRAM_D_ena <= 1; // be ready for writing
if (rs232in_attention) begin
oSRAM_ADSC_N <= 0;
oSRAM_A <= wp;
oSRAM_GW_N <= rs232in_read_data == 48;
SRAM_D <= rs232in_read_data; // WRITE!
state <= 10;
if (rs232in_read_data != 48)
wp <= wp + 1;
else begin
wp <= 0;
state <= 0;
end
rp <= 0;
end
end
......
1: begin // wait a cycle just in case
state <= 2;
SRAM_D_ena <= 0; // Turn off the drivers
oSRAM_OE_N <= 0; // Open the SSRAM drivers
end
2: begin // issue read
oSRAM_ADSC_N <= 0;
oSRAM_A <= rp;
rp <= rp + 1;
state <= 3;
end
3: state <= 4; // READ latency
4: state <= 5; // READ latency
5: begin
// receive data
rs232out_write_data <= SRAM_DQ; // READ!
rs232out_write_enable <= 1;
state <= 6;
end
See the attachment for a full example for the DE2-70. If someone in the Santa Clara area could lend me a Cyclone III kit, I could probably adopt it to that.
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