32-bit SSRAM must have byteenable for Nios II?

I know it's a bit old thread but still... Byteenable's for NIOS are important if you're using EPCS or equivalent device to boot FPGA and SW code. Since Flash devices(serial) are usually 8 bit wide, the bootloader packs the SSRAM using byte enables... so if you don't have them connected or misconnected the processor will fail to run although the FPGA boots correctly.

FWIW, a late follow up: the most recent version of YARI uses the SSRAM for the main memory and framebuffer, so this is pretty thoroughly tested. Check out the most recent version on http://repo.or.cz/w/yari.git

HI,

Hmm, I got the following silly example working on DE2-70, but haven't yet written a more robust memory control, assigned timing constraints, used a PLL, or used the burst mode. Also, I don't have the Cyclone III kit, so it'll likely take some adoption to get it running.

   assign oSRAM_CLK = iCLK_50;
   assign oSRAM_ADSP_N = 1; // We use ADSC#
   assign oSRAM_BE_N   =~0; // byte write enable
   assign oSRAM_CE1_N  = 0; // chip enable
   assign oSRAM_CE2    = 1; // chip enable
   assign oSRAM_CE3_N  = 0; // chip enable
   reg        SRAM_D_ena   = 0;
   reg  SRAM_DPA_out = 0;
   reg  SRAM_D       = 0;
   assign SRAM_DPA = SRAM_D_ena ? SRAM_DPA_out : 4'hZ;
   assign SRAM_DQ  = SRAM_D_ena ? SRAM_D       : 32'hZ;
   /* Demo state machine: When we get a serial char, we add it to the buffer
      and prints the whole buffer again */
   reg  state = 0;
   reg  wp = 0;
   reg  rp = 0;
   always @(posedge iCLK_50) begin
      // Set up default values so that writes below are one-shot
      oSRAM_ADSC_N <= 1;
      oSRAM_GW_N   <= 1;
      oSRAM_ADV_N  <= 1;
      oLEDR <= state;
      case (state)
      0: begin // wait for input
         oSRAM_OE_N <= 1;  // close the SSRAM DQ drivers
         SRAM_D_ena <= 1;  // be ready for writing
         if (rs232in_attention) begin
            oSRAM_ADSC_N <= 0;
            oSRAM_A      <= wp;
            oSRAM_GW_N   <= rs232in_read_data == 48;
            SRAM_D       <= rs232in_read_data; // WRITE!
            state        <= 10;
            if (rs232in_read_data != 48)
               wp        <= wp + 1;
            else begin
               wp        <= 0;
               state     <= 0;
            end
            rp           <= 0;
         end
      end
......
      1: begin // wait a cycle just in case
         state      <= 2;
         SRAM_D_ena <= 0; // Turn off the drivers
         oSRAM_OE_N <= 0; // Open the SSRAM drivers
      end
      2: begin // issue read
            oSRAM_ADSC_N <= 0;
            oSRAM_A      <= rp;
            rp           <= rp + 1;
            state        <= 3;
         end
      3: state <= 4; // READ latency
      4: state <= 5; // READ latency
      5: begin
         // receive data
         rs232out_write_data <= SRAM_DQ; // READ!
         rs232out_write_enable <= 1;
         state <= 6;
      end

Hi,

Srinath, it would be useful to know what you tried and where you got stuck.

Hi,

Does NIOS II have the option of write back data caches with miss-allocate? If so, the need for byte enables evaporates.

You are correct. The performance impact this will have depends on your system and software design. Your processor will not necessarily run half as fast. The data and instruction caches will hide some of the performance loss. Any instruction that directly accesses the memory will suffer from an extra cycle penalty.