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Altera_Forum
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18 years ago

32-bit SSRAM must have byteenable for Nios II?

One question - For 32-bit external SSRAM (or async. SRAM), does it have to have byte write mode enabled in order to work with Nios II processor? In other words, can Nios II handle all instruct...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Srinath, it would be useful to know what you tried and where you got stuck.

Did you read the datasheet? (http://www.issi.com/pdf/61vps_lps25636a_51218a.pdf)

Pay especially attention to the figure on page 18.

You should feed the ssram a 180 degree shifted clock. Simply

assign ssram_clk = ~clk;

may work, but the proper way is to use a pll to generate ssram_clk.

Keep ADSP#, CE, ADV# high, and CE#, CE2# low.

To read one word, set ADSC# low and present the address for _one_ cycle. Keep OE# low. You can pick up the data on DQ in two cycles.

To write, turn OE# high, wait a cycle, drive the data to DQ, present the address, and set ADSC# and GW# low for one cycle.

If this isn't enough, I'm working on a small demo for the ssram on the DE2-70 kit that I can post later. The same should work for you kit with minor modifications.