One question - For 32-bit external SSRAM (or async. SRAM), does it have to have byte write mode enabled in order to work with Nios II processor? In other words, can Nios II handle all instructions and data exclusively in 32-bit mode? If my program uses data type of 16-bit or 8-bit, how is it handled if I don't have byte mode enabled? How about 16-bit external memory? Can it work with Nios without byte write mode enabled? Thanks for your help in advance!!!

If you plan to write less than a full word (32 bits) at a time then you must have the byte enables. The NIOS expects it's instruction and data memories to be byte addressable. If you are going to use the SRAM as instruction or data memory for the NIOS then you must connect the byte enables. This is the only mechanism available to the processor for performing byte-addressed writes to an interface that is greater than 8-bits wide. The only way you could get around it would be to do a read-modify-write every time you wanted to write less than 32-bits. Read the data from the SRAM, modify the byte(s) that are being written to and write the data back out. This is a huge inefficiency (defeats the purpose of using SRAM in the first place) and you would have to write your own controller to do this as it would have to be transparent to the processor. If you are not going to use the SRAM for NIOS instruction or data memory; that is if you are going to use it for your own purposes and you will control the writing of data to the memory, then you could certainly only do 32-bit writes if it fits your design needs. I assume your motivation is to save pins. Jake

Jake - Thanks a lot. Yes, you are absolutely right, the goal is to save a few IO pins. Unfortunately, I plan to use external SRAM for instructions and data. To be byte addressable, given the constraint of IO pins, it seems that now I have to reduce data bus width from 32-bit to 16-bit (by using 16-bit SRAM). If I do that, I assume my system performance will be reduced by half (rougly) -- due to the reason that for each 32-bit instruction, CPU has to fetch twice instead of once. Is that right? Thanks again for your help!! FZ

You are correct. The performance impact this will have depends on your system and software design. Your processor will not necessarily run half as fast. The data and instruction caches will hide some of the performance loss. Any instruction that directly accesses the memory will suffer from an extra cycle penalty. Jake

Does NIOS II have the option of write back data caches with miss-allocate? If so, the need for byte enables evaporates.

Hi, Could you please provide me how to read and write in to SSRAM on the Nios II Evaluation Board (Cyclone III EP3c25F324C6) . I am not using Nios for my project , So please guide me how to wrte and read in to SSRAM with out NIOS II Processot. Hope you reply soon. Thanks , Srinath.

32-bit SSRAM must have byteenable for Nios II?

12 Replies

Altera_Forum
Honored Contributor
17 years ago
FWIW, a late follow up: the most recent version of YARI uses the SSRAM for the main memory and framebuffer, so this is pretty thoroughly tested. Check out the most recent version on http://repo.or.cz/w/yari.git

It's currently just using the SSRAM at 50 MHz, but pending changes pushes it close to 200 MHz.

(*) YARI is a MIPS I compatible soft core + peripherals for the DE2-70 and others. All logic is written from scratch by me, including all peripherals and memory controllers.

Tommy
Altera_Forum
Honored Contributor
17 years ago
I know it's a bit old thread but still... Byteenable's for NIOS are important if you're using EPCS or equivalent device to boot FPGA and SW code. Since Flash devices(serial) are usually 8 bit wide, the bootloader packs the SSRAM using byte enables... so if you don't have them connected or misconnected the processor will fail to run although the FPGA boots correctly.

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32-bit SSRAM must have byteenable for Nios II?

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