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Altera_Forum's avatar
Altera_Forum
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17 years ago

30 ~ 40mins runtime NIOS PIO fails

Hi,

I have a issue with the PIO's... I used the PIOS to gather sensor data from a fifo buffer.. this runs very well pooling 24 sensor data from a buffer at 3msec X 24sensors... The problem is after 30mins or so the PIO just stop detecting the specific sensor and stop updating the respective DAC for 400msec, and then start functioning perfectly again... IN this 400msec silence, the PIO reliably service the rest of the sensor... I have put probes on the buffer and the PIO of the NIOS and its actually gets the data and I am pretty sure that the specific sensor data address comes in the buffer and comes out of the buffer and to the NIOS PIO..

IS there any issue in using the PIO that I should be awareof?...

I also tried using the avalon fabric to get the data for me instead of PIO.. The ports from the avalon is 16 bit readdata and 1 read line... I tried putting a simple program to pulse the read line with IORD(X,X) but it doesn't toggle at all... PLease advise... I am running out of ideas on how to resolve this problem.

rgds,

Lanz

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    @LANZONES

    Can you provide more info on your setup and software?

    Do you use interupts in your software, are you polling the PIO's, do you have other tasks where your Nios could be busy?

    Is the fysical connection and voltage levels between your ADC's and FPGA OK?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hi,

    this is the diagram for our FPGA 2... the inputs came from the optos at high speed.. all nios pios are use internally. and external pins are reference to 3.3V supply... The problem is the 1x9bit PIO input.. I confirmed that the specific sensor in question is present to the NIOS II block by probing this 1x9bit PIO input when the 200msec latency occurs... the mbus is not enabled and no other task excpt servicing this 1x9bit PIO input... 1x9bit PIO input is not interrupt enable... This is being pooled after the SM Read Req block have received a 1bit signal from the NIOS 2 block...the SM Read Req block will then trigger on clock to read the fifo thru rdReq line..

    rgds

    lanz
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Isolate your NIOS-II pio from the rest of your circuit and your code and see if it works alone. If yes, there is something wrong with your control logic such as SM Trig Read Req.