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Altera_Forum's avatar
Altera_Forum
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15 years ago

16MHz crystal and PLL or 64MHz crystal?

I'm using a Cyclone II (EP2C5T144C8 to be precise).

It's being interfaced to an external chip B.

External chip B communicates with the FPGA over LVDS, and supplies both data and a clock through LVDS. The clock supplied is 64MHz.

In the FPGA I use the 64MHz clock as supplied by chip B as my main reference clock.

Now, I can choose to either:

a. Use a 100ppm 64MHz HCMOS crystal oscillator that I connect only to chip B in its clock input (not to the FPGA directly), which then supplies this clock to my FPGA over LVDS alongside the LVDS datalines.

b. Or use a 25ppm 16MHz HCMOS crystal oscillator that I connect to the spare PLL in my FPGA (using a single input pin) which multiplies the signal by 4 to generate 64MHz out of it, which is then escorted off-chip over LVDS to chip B on its clock input, which subsequently uses that to supply back to the same FPGA the phase corrected 64MHz reference clock through LVDS alongside the LVDS datalines.

What are the pros and cons of either solution?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    After some consideration I decided to go with the direct 64MHz approach, even invest in a more expensive crystal (64MHz 25ppm), in order to avoid harmonics in my RF circuits (now I have to deal with 64MHz harmonics, and not with 16MHz harmonics plus whatever the PLL generates due to the multiplication by a factor of four).

  • Altera_Forum's avatar
    Altera_Forum
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    If the design uses a single clock domain only, supplying this clock frequency directly isn't a bad idea, although a high frequency crystal oscillator usually involves a higher supply current. If the design is utilizes multiple clock domains and uses a PLL anyway, I usually go for a low frequency, e.g. 16 MHz clock.

    In cases, where a low jitter clock is required, e.g. for a digital receiver's ADC clock, it should not be degraded by the FPGA clock tree generally, and the internal PLL in particular.