Altera_Forum
Honored Contributor
15 years ago16MHz crystal and PLL or 64MHz crystal?
I'm using a Cyclone II (EP2C5T144C8 to be precise).
It's being interfaced to an external chip B. External chip B communicates with the FPGA over LVDS, and supplies both data and a clock through LVDS. The clock supplied is 64MHz. In the FPGA I use the 64MHz clock as supplied by chip B as my main reference clock. Now, I can choose to either: a. Use a 100ppm 64MHz HCMOS crystal oscillator that I connect only to chip B in its clock input (not to the FPGA directly), which then supplies this clock to my FPGA over LVDS alongside the LVDS datalines. b. Or use a 25ppm 16MHz HCMOS crystal oscillator that I connect to the spare PLL in my FPGA (using a single input pin) which multiplies the signal by 4 to generate 64MHz out of it, which is then escorted off-chip over LVDS to chip B on its clock input, which subsequently uses that to supply back to the same FPGA the phase corrected 64MHz reference clock through LVDS alongside the LVDS datalines. What are the pros and cons of either solution?