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Altera_Forum
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15 years ago

16MHz crystal and PLL or 64MHz crystal?

I'm using a Cyclone II (EP2C5T144C8 to be precise). It's being interfaced to an external chip B. External chip B communicates with the FPGA over LVDS, and supplies both data and a clock through ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

If the design uses a single clock domain only, supplying this clock frequency directly isn't a bad idea, although a high frequency crystal oscillator usually involves a higher supply current. If the design is utilizes multiple clock domains and uses a PLL anyway, I usually go for a low frequency, e.g. 16 MHz clock.

In cases, where a low jitter clock is required, e.g. for a digital receiver's ADC clock, it should not be degraded by the FPGA clock tree generally, and the internal PLL in particular.