Forum Discussion
dynamite1981
New Contributor
New Contributor128GB DRAM configuration problem with CXL IP
We are running into an issue when trying to upgrade the DRAM capacity of the Agilex 7 CXL-enabled FPGA. We are following the guide called "Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA I...
RongY_altera
Contributor
ContributorHi,
Since you're using a larger DDR, please confirm you've updated EMIF settings. After this, you may need to update data width for MC Top and other related modules.
Regards,
Rong
