128GB DRAM configuration problem with CXL IP

We are running into an issue when trying to upgrade the DRAM capacity of the Agilex 7 CXL-enabled FPGA. We are following the guide called "Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP Design Example User Guide" V 1.16 (updated for Quartus Prime 25.1, IP version 1.16),  Appendix B "Updating HDM Size".

In particular, when we try the 128G design, using the parameters in Table 47, we successfully boot the machine and can use `numactl --hardware` to read that the Linux kernel is interpreting it as a 128G CPUless NUMA node. However, when we map the CXL memory (using /dev/mem) and begin to read and write to it, we see that in reality, there appears to only be 16G looped 8 times. In other words, if we write to address 0, and then read from address 16*2^30 or 32*2^30, we get back the same value.

It seems like we must not be updating a parameter that increases the address bitwidth, but we have made all of the modifications as described in the appendix and tried a COE-disabled version.

For context, we are running our 128G design in a 2x64G DIMM configuration rather than using a single 128G stick (DDR4 doesn't officially support 128G sticks). Is this the correct configuration? We ask because the board came with only 1x16G, and we aren't sure if the hardware/IP is capable of automatically recognizing the second DIMM or if additional configuration is required.