Forum Discussion
2reSolve
New Contributor
2 years agoHello Naim,
Thanks for your attantion on this issue. Any info you may share which would help resolve this issue will be greatly appreciated.
Meanwhile, as per FvM suggestions, we will have an FPGA expert characterize and observe the function failure in detail, review the original design for possible timing constraint vacancies and other trap doors. Hopefully this will bring a solution to our problems.
Best, Tore