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Luke_J1986
New Contributor
New Contributor10AX115N3F40E2SG DDR test fail
We have 3 normally used PCBA. The FPGA parts is 10AX115N3F40E2SG , 2020+ datecode .We removed it and replaced it with 2023+datecode. However, we found that the DDR function test could not pass. May I...
Hi Luke_J1986 ,
I don't think there is any silicon changes other than IP fixes during that time.
You may try below suggestion to identify the problem:
- Confirm identical .sof/.pof and Quartus version were used before/after swap.
- Check whether the failure is at DDR calibration/training or later memory traffic.
- Compare supply rails during DDR init: core, VCCIO, VREF, VTT.
- Inspect BGA rework quality on the FPGA and nearby DDR components.
- Try the 2023 part on the other 2 known-good PCBAs to see whether the failure follows the chip or stays with the board.
- If possible, reduce DDR speed or relax margin to see whether it becomes stable.
Regards,
Adzim
AdzimZM_Altera
Regular Contributor
Regular ContributorHi Luke_J1986 ,
I don't think there is any silicon changes other than IP fixes during that time.
You may try below suggestion to identify the problem:
- Confirm identical .sof/.pof and Quartus version were used before/after swap.
- Check whether the failure is at DDR calibration/training or later memory traffic.
- Compare supply rails during DDR init: core, VCCIO, VREF, VTT.
- Inspect BGA rework quality on the FPGA and nearby DDR components.
- Try the 2023 part on the other 2 known-good PCBAs to see whether the failure follows the chip or stays with the board.
- If possible, reduce DDR speed or relax margin to see whether it becomes stable.
Regards,
Adzim
