Yocto build with time limited IP core in sof file
Hello,
We bought a Stratix-10 Development kit - DKSOC1ssxLD with Part no. 1SX280LU2F50E1VG , L-tile. While doing a yocto build of a vendor supplied design , I am
getting the following error:
Error (210039): File fpga_hps_auto.sof contains one or more time-limited IPs that support the Intel FPGA IP Evaluation Mode feature that will not work after the hardware evaluation time expires. Refer to the Messages window for evaluation time details.
In the synthesis messages, I see the following:
Warning(18392): "SerialLite III Streaming" will use the Intel FPGA IP Evaluation Mode feature
The design in question uses Stratix-10 part number : 1SX280HN2F43I2LG , H-tile
Is there an extra charge to use "SerialLite III Streaming" IP core?
Or is this arising from the fact the license we got from the purchase of dev kit that has L-tile part?
If so, can we get a trial license for the H-tile part? Is there anyway to upgrade our license?
Thanks,
Mohan