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Thulasi's avatar
Thulasi
Icon for New Contributor rankNew Contributor
15 days ago

Why 390.625MHz clock to F-Tile Reference fequency

Hi,

This question is regarding the Agilex 7 M-Series FPGA Development Kit.

In the evaluation board schematics, the Si5518 provides a 390.625 MHz clock that is connected to two F-Tile reference clock inputs.

From the F-Tile Ethernet Hard IP User Guide, I understand that standard Ethernet designs typically use 156.25 MHz as the PMA reference clock, while the 390.625 MHz clock appears internally as the clk_txmac/clk_rxmac clock.

My questions are:

1. Which F-Tile configuration or interface is intended to use the external 390.625 MHz reference clock on the development board?

2. Is this reference intended for the Ethernet Hard IP, PMA Direct mode, SyncE, or some other transceiver application?

3. Are there any official reference designs that use this 390.625 MHz reference clock?

I would appreciate it if you could clarify the intended use of this clock on the Agilex M Development Kit.

Regards,

Fpga Devkit

1 Reply

  • paveetirrasrie_Altera's avatar
    paveetirrasrie_Altera
    Icon for Frequent Contributor rankFrequent Contributor
    3 hours ago

    Hi Thulas,

     

    Based on the documents, the 390.625 MHz clock from the Si5518 on the Agilex 7 M-Series development kit is not meant to be the standard F-Tile Ethernet PMA reference clock.

    For F-Tile Ethernet Hard IP, the usual PMA reference clock is:

    • 156.25 MHz for standard Ethernet modes
    • 312.5 MHz or 322.265625 MHz only for some specific FGT cases without AN/LT

    So to answer your questions:

     

    1. The external 390.625 MHz clock on the M-Series board seems to be there mainly for timing-related use cases such as IEEE 1588 TOD/PTP, and also for board-level SyncE/CPRI style clocking, rather than as the normal Ethernet PMA refclk.
    2. For Ethernet Hard IP, 390.625 MHz lines up with the TOD clock requirement in basic timestamp accuracy mode. It also matches the internally generated o_clk_tx_div and o_clk_rec_div clocks for many Ethernet rates. So it makes more sense as a timing or transceiver support clock than as the main PMA reference input.

    So the short version is:

    • use 156.25 MHz as the normal F-Tile Ethernet Hard IP PMA reference clock unless your selected FGT mode specifically allows one of the alternate documented refclk values
    • treat the on-board 390.625 MHz clock as mainly intended for PTP/TOD, SyncE/CPRI, or related timing/transceiver use cases, not as the default Ethernet PMA reference clock

    Regards,

    pavee