Why 390.625MHz clock to F-Tile Reference fequency

Hello Thulasi,

1. Purpose of the Si5518 390.625 MHz reference into the Si5395/Si5391 distribution network

390.625 MHz is the standard parallel-clock frequency for F-Tile Ethernet at 25G/50G/100G/200G/400G rates. The divided clock output o_p0_clk_tx_div supports 156.25 MHz for 10GE, 312.5 MHz for 40GE, and 390.625 MHz for all other Ethernet modes. Agilex 7 · Transceiver/PHY It is also the required TOD (Time-of-Day) clock frequency for PTP and SyncE applications at those rates. The TX TOD input clock i_clk_tx_tod frequency varies based on the Ethernet rate and timestamp accuracy mode in Basic timestamp accuracy mode it is 390.625 MHz for 25GE/50GE/100GE/200GE/400GE. Agilex 7 · Clock

The Si5518 is a jitter-attenuating clock IC well-suited to SyncE/PTP applications. By generating a clean, low-jitter 390.625 MHz output, it provides a single high-quality frequency anchor from which the Si5395 and Si5391 (wideband jitter-attenuating synthesizers) can derive all the other interface clocks needed on the board DDR5 reference, HBM UIB PLL reference, NoC PLL reference, SDM clock, and the Ethernet/SyncE clocks through integer or fractional division/multiplication.

2. Why is this clock distributed to DDR5, HBM, and SDM circuitry?

The Si5395/Si5391 are not passing 390.625 MHz directly to those interfaces. They use it as their input reference and synthesize the correct output frequencies for each downstream consumer. For example:

The ref_clk signal for the Agilex 7 M-Series EMIF IP DDR5 Component variant is the reference clock used by the EMIF PLL. Agilex 7 · General That PLL reference has its own required frequency (not 390.625 MHz directly), which the Si5395/Si5391 generate from the 390.625 MHz input.

Similarly, the HBM2E UIB PLL and the NoC PLL each require their own dedicated reference clocks, requiring a pin location assignment for the NoC PLL (one for top and one for bottom hard memory NoC) and the UIB PLL (one for top and one for bottom HBM2E), plus a pin location for the reference clock of the EMIF PLL for any EMIF IP instance. Planning NoC PLL and I/O PLL

There is no connection between the SDM and the hard memory NoC, and all signals from the SDM bypass the hard memory NoC Agilex 7 · EMIF/DDR so the SDM clock path is independent and the Si5391/Si5395 simply synthesize the appropriate SDM reference from the same 390.625 MHz source.

Using a single upstream reference for all synthesizers simplifies board design and ensures all generated clocks are frequency-coherent (traceable to a common source), which is important for SyncE operation.

3. Is 390.625 MHz chosen as a convenient common reference, or is there a specific architectural reason?

Both, actually. 390.625 MHz is architecturally significant for F-Tile Ethernet/SyncE/PTP it is not an arbitrary choice. For 25G/50G Ethernet, the minimum supported clock rate for MAC client asynchronous FIFO operation is 390.625 MHz. Agilex 7 · Clock Using it as the board-level reference means the Si5518 output can be routed directly (or with minimal buffering) to the F-Tile TOD/SyncE clock inputs, while the Si5395/Si5391 simultaneously derive all other required frequencies from it. This avoids needing a second independent reference oscillator for Ethernet timing, which would complicate SyncE holdover and traceability.

The 390.625 MHz value is also integer-related to 156.25 MHz (÷2.5, or equivalently ×2.5), which is the standard F-Tile PMA reference clock frequency. The PMA reference clock is driven by the F-Tile Reference and System PLL Clocks IP; 156.25 MHz is the recommended frequency for all Ethernet modes and is the only supported frequency when using FHT PMA or when auto-negotiation and link training is enabled. Agilex 7 · Transceiver/PHY The Si5395/Si5391 can cleanly divide 390.625 MHz to produce 156.25 MHz (÷2.5) or other required frequencies.

4. Is this kit-specific, or is it the recommended architecture for customer designs?

The evaluation kit's clocking topology a jitter-attenuating SyncE-capable PLL (Si5518) feeding wideband synthesizers (Si5395/Si5391) that fan out to all major clock domains is a well-established board design pattern for designs that combine Ethernet/SyncE/PTP with HBM and DDR5. The Agilex 7 FPGA M-Series Development Kit (HBM2e Edition, 3x F-Tile & 1x R-Tile) offers programmable clocking with Si5391, Si5392, Si5395, Si5332, and Si5518. Agilex 7 · General The kit is explicitly designed to demonstrate this kind of multi-domain clocking.

For customer designs combining these interfaces, the key architectural principles to carry over are:

Use a single low-jitter, SyncE-traceable reference (e.g., Si5518 or equivalent) as the upstream anchor.

Use jitter-attenuating synthesizers (Si5395/Si5391 class) to fan out to each interface's PLL reference pin, keeping all clocks frequency-coherent.

Each F-tile system must instantiate one F-Tile Reference and System PLL Clocks IP Ethernet , so your board must supply the appropriate reference to each F-tile's clock input.

Using a single TOD clock for multiple 25GE Ethernet IP instances violates the F-Tile Ethernet Hard IP requirement for separate TOD clocking Agilex 7 · Ethernet so your synthesizer fan-out must provide independent TOD clock paths per port when PTP is enabled.

Hope this helps.

Regards,

Pavee