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SZhou22's avatar
SZhou22
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6 years ago

voltage toleration for the high Z state

What is the voltage toleration for IO pin high Z state of FPGA/CPLDs? Would 15V damage the chip?

6 Replies

    • SZhou22's avatar
      SZhou22
      Icon for New Contributor rankNew Contributor
      6 years ago
      Sorry，the Internet sucks due to some reasons.  Can you answer my question about the toleration of highs state？ Take MAX V series for example. 发自我的iPhone
  • Rahul_S_Intel1's avatar
    Rahul_S_Intel1
    Icon for Frequent Contributor rankFrequent Contributor
    6 years ago

    Hi ,

    To explain to you , with respect to max 5 , I am attaching absolute maximum rating and recommended operating conditions , these are the values which FPGA can tolerate.

    The 15V will damage the FPGA