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User1579503626260295's avatar
User1579503626260295
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6 years ago

Vih and Vil parameters are not mentioned for the LVPECL input voltage in the FPGA Arria V datasheet.

I am working on the signal integrity using hyperlynx for the FPGA Arria V GX. I am performing one simulation for the LVPECL input voltage to the FPGA in which I got the Vih=2.38 V and Vil= 1.63 V. But in datasheet of Arria V, these Vih and Vil parameters are not mentioned. In comment section they mention for data rate less than 700 Mbps the input voltage range should be within 0.45 V to 1.95 V. Can you please clarify whether it is a input voltage swing or voltage high and low logic limit?

Also for LVPECL they mention VID= 300 mV min. Is this single ended swing or differential swing?

Please find the attachment for the reference.

3 Replies

  • User1579503626260295's avatar
    User1579503626260295
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi Bruce,

    Thanks a lot for your response.

    Actually I mentioned two specifications in which I have a doubt. Can you be more specific which specification you are talking about ?

    Thank you.

  • YuanLi_S_Intel's avatar
    YuanLi_S_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Sorry for being not very clear. The datasheet that you have shown is actually referring to differential pair. Differential pair doesn't have VIH and VIL. What you need to focus on for differential pair is VID and VCM for input differential pair and VOD and VOCM for output differential pair.