Tx_parellel_data does not match Rx_parellel_data

Hi,

As I understand it, you observe some problem where the RX parallel data output is not matching your TX parallel data input. As I look into yoru signaltap, I understand that you are enabling the internal serial loopback. Therefore, we can isolate any potential signal integrity problem.

I notice that the tx_digitalreset = 1 which means that the TX PCS blocks are still in reset mode. Would you mind to look into this? For the TX to work, all the reset signal should be released.

Just wonder if you are using the transceiver reset controller in your design?

It is recommended for your to perform Modelsim simulation to isolate any functional problem prior to hardware debugging.

To ease the debugging, I would recommend you to start with simple design with minimal data width and minimal data rate. Once it is working, then you slowly increase the data rate and data width. Attached is a simple A10 design previously from wiki for your reference.

Please let me know if there is nay concern. Thank you.

Hi,

tx_digitalreset issue is solved. i have disabled bitslip

1) my rx parallel data keep on changing ,where there is no change is tx parallel data, nor bitslip is implemented.

when this behavior will occur ? is it normal behavior ?

2) I am using dynamic reconfiguration to change profiles,

in simulation it is working fine i can see pll_locked =1, and frequency is also changing.

BUT on board PLL_locked is always 0.

Hi,

Thanks for your update. As I understand it, now you are observing two different problems:

1. RX parallel data not staying at constant

2. TX PLL no lock after reconfiguration

To facilitate debugging, we shall focus on the first problem first. I notice from your signaltap that the serial loopback enable = 0. I believe you are using external loopback from TX to RX.

Just to check with you on the following:

1. Have you had a chance to run Modelsim simulation with your test design to see if it is working fine?

2. Can you share with me a simple test design of yours? I would like to look into the Native PHY to understand your configuration.

3. In your test design, just wonder if you assert the serial loopback, do you still see the same observation where RX parallel data is not constant?

4 Just wonder if you have a chance to test with the previous simple test design shared by me?

Please let me know if there is any concern. Thank you.

Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.