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Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Tx_parellel_data does not match Rx_parellel_data

Hi, I am using arria10 development kit for my project. In my project i am using transceivers and speed is 10gbps. Connections are made by referring transceiver user guide. All signals are prope...
Rk_Athram's avatar
Rk_Athram
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Hi,

tx_digitalreset issue is solved. i have disabled bitslip

1) my rx parallel data keep on changing ,where there is no change is tx parallel data, nor bitslip is implemented.

when this behavior will occur ? is it normal behavior ?

2) I am using dynamic reconfiguration to change profiles,

in simulation it is working fine i can see pll_locked =1, and frequency is also changing.

BUT on board PLL_locked is always 0.