Occasional Contributor
Regular ContributorHi,
As I understand it, you observe some problem where the RX parallel data output is not matching your TX parallel data input. As I look into yoru signaltap, I understand that you are enabling the internal serial loopback. Therefore, we can isolate any potential signal integrity problem.
I notice that the tx_digitalreset = 1 which means that the TX PCS blocks are still in reset mode. Would you mind to look into this? For the TX to work, all the reset signal should be released.
Just wonder if you are using the transceiver reset controller in your design?
It is recommended for your to perform Modelsim simulation to isolate any functional problem prior to hardware debugging.
To ease the debugging, I would recommend you to start with simple design with minimal data width and minimal data rate. Once it is working, then you slowly increase the data rate and data width. Attached is a simple A10 design previously from wiki for your reference.
Please let me know if there is nay concern. Thank you.
