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Altera_Forum's avatar
Altera_Forum
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18 years ago

Triple speed ethernet and Marvell Phy on Stratix III

Hi..

Need help here!! I've been struggling for a couple weeks.

I have a stratix III board with a on-board Marvell PHY.

I just tried to make a triple speed ethernet working on MII mode (10/100 is good enough, i don't need high speed.)

So i just take CycloneIII's example (from its development kit) as a reference for the SOPC and follow the manual of TSE.

Also I add a redundunt reset circuitry for this enet_reset since there is a certain issue on this kind of setup which i got from this forum.

However, it never worked.

Symton is as follows.. BTW i use Simple socket server on NIOSII and Quartus8.0 SOPC.

PHY can receiver packet (it seemed.. because i can see RX LED is blinking when i tried 'ping').. but no Tx ( i never see TX LED blinking.)

Also i set a break point on SGDMA rx int.. it never asserted.

So i guessed TSE_MAC never receives data from PHY.

I know there should be some tools which could verify something for me.. Sorry.. I'm a newbid in Altera FPGA.

So if you think there is anything i should check or modify.. Please let me know. Of course, if you make it work before, could you please share that with me?

Thanks.

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  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I don't think so... as long as the reset pulse is larger than Marvell's specification it should be fine. And if you can communicate with your PHY's MDIO, I would say that the initialization went fine.

    Can you check with an oscilloscope the clock signals from the PHY? It should tell you if the problem is in the FPGA or outside.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I was thinking about that too.. If that's the reason, i can have a break here.

    However, after i borrowed one ossiloscope and checked that 25Mhz crystal output, unfortunetely it's there.. so the problem should be coming from FPGA?

    Any suggestions?
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I'm starting to be out of suggestions ;)

    Can you check the enet_rx_clk and enet_tx_clk signals with your oscilloscope? It may be a bit tricky to catch with BGA's though...
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the reply:)

    I've already started to ask help from FAE.

    (I suspected there is hardware issue as well.)

    Hopefully they can come out with something soon.

    Will update u soon.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Please post any resolution you get on this issue. We seem to be stuck near the same point.

    -Art
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Finally get it work with the support from FAE.. Just want to mention that design should be pretty straight-forward as specified on other threads. Two things are more critical.

    1. timing constraints.. (it's less critical than 2.)

    2. MDIO programming to reset PHY.. this is a must to make Stratix III board's Phy starting to work. Also rx and tx clocks won't start until you do the follows.

    I just provide the patch as follows.. please add the following lines at 1233 of altera_avalon_tse.c.. you should be able to locate this file under altera\80\ip\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\HAL\src

    /***********************************/

    if ((is_phy_in_profile == 1) && (oui == 0x5043) && (phyadd == 0x12))

    {# ifdef STRATIX_III_3S150_GMII//switch to GMII mode

    alt_tse_phy_wr_mdio_reg(pphy, 27, 0, 4, 0xf);// switch to GMII mode

    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1, 1);//reset PHY

    while ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1)) != 0); //wait reset complete# endif

    # ifdef Stratix_III_3S150_SGMII//switch to SGMII mode

    alt_tse_phy_wr_mdio_reg(pphy, 27, 0, 4, 0x0);// switch to SGMII mode

    alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1, 1);//reset PHY

    while ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1)) != 0); //wait reset complete# endif

    }

    Hopefully this can help you to bring your own Stratix III board..
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    hi, i think i have a quite similar problem to my stratix II gx. where can i find code to my board?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    i can't find any macro called " Stratix_III_3S150_SGMII " in my pc, i have a stratix 2 GX, what macro i should use?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Hey.. man,

    Just add a definition in the header of file yourself to make the macro alive. Just make sure which mode you want to turn it on.

    Leon.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    Finally get it work with the support from FAE.. Just want to mention that design should be pretty straight-forward as specified on other threads. Two things are more critical.

    1. timing constraints.. (it's less critical than 2.)

    --- Quote End ---

    Thanks Leon. Would you mind posting your timing constraints? I'm trying to use GMII interface (Marvell Phy, StratixIII devkit, tse IP), but I'm having a real hard time figuring out what the constraints need to be.

    -Brian