Honored Contributor
Honored ContributorFinally get it work with the support from FAE.. Just want to mention that design should be pretty straight-forward as specified on other threads. Two things are more critical.
1. timing constraints.. (it's less critical than 2.) 2. MDIO programming to reset PHY.. this is a must to make Stratix III board's Phy starting to work. Also rx and tx clocks won't start until you do the follows. I just provide the patch as follows.. please add the following lines at 1233 of altera_avalon_tse.c.. you should be able to locate this file under altera\80\ip\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\HAL\src /***********************************/ if ((is_phy_in_profile == 1) && (oui == 0x5043) && (phyadd == 0x12)) {# ifdef STRATIX_III_3S150_GMII//switch to GMII mode alt_tse_phy_wr_mdio_reg(pphy, 27, 0, 4, 0xf);// switch to GMII mode alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1, 1);//reset PHY while ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1)) != 0); //wait reset complete# endif # ifdef Stratix_III_3S150_SGMII//switch to SGMII mode alt_tse_phy_wr_mdio_reg(pphy, 27, 0, 4, 0x0);// switch to SGMII mode alt_tse_phy_wr_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1, 1);//reset PHY while ((alt_tse_phy_rd_mdio_reg(pphy, TSE_PHY_MDIO_CONTROL, TSE_PHY_MDIO_CONTROL_RESET, 1)) != 0); //wait reset complete# endif } Hopefully this can help you to bring your own Stratix III board..
