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Altera_Forum's avatar
Altera_Forum
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17 years ago

Triple speed ethernet and Marvell Phy on Stratix III

Hi.. Need help here!! I've been struggling for a couple weeks. I have a stratix III board with a on-board Marvell PHY. I just tried to make a triple speed ethernet working on MII mode (10/10...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I don't think so... as long as the reset pulse is larger than Marvell's specification it should be fine. And if you can communicate with your PHY's MDIO, I would say that the initialization went fine.

Can you check with an oscilloscope the clock signals from the PHY? It should tell you if the problem is in the FPGA or outside.