Struggling with the (mSG)DMA Controller Core

Question

Still relatively new to FPGA development and I am currently working with the Intel Stratix SX 10. I was wondering if anyone knows how to connect the DMA Controller Core in the GSRD version 19.1 found here: https://rocketboards.org/foswiki/Documentation/ReleaseNotesAndContentsLTS

I guess what I'm asking is if there is an example that shows how the (mSG)DMA Controller Core is connected in the Platform Designer.

Thanks in advance!

ahmed_h_intel1 · Answer

Hi,

There are some available examples for using the Modular Scatter Gather DMA. Please check the following examples:

1- https://fpgacloud.intel.com/devstore/platform/12.1/Standard/modular-sgdma-video-frame-buffer/

2- https://fpgacloud.intel.com/devstore/platform/12.1/Standard/modular-sgdma/

3- https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/hyperram-msgdma-reference-project/

4- https://fpgacloud.intel.com/devstore/platform/17.0.0/Standard/hyperram-msgdma-reference-project-for-ebv-hypermax-board/

5- https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/max10-10m50-development-kit-ghrd-with-nios-iiddr3qspi-flashethernetmsgdmauartadc-with-linux/

Please let me know if you need more help?

Regards,

ajung123 · Answer

Hi,Sorry, I should have been more clear. I want to connect the DMA similarly to this configuration (which is for the Cyclone V): http://blog.reds.ch/?p=835 and add this configuration onto the GSRD I linked. I want to have the FPGA's DMA is connected to the hard processor of the Stratix 10 and then confirm the connection is correct by writing and reading data. The issue I am running into is that the (mSG)DMA require Avalon ports while the hard processor only has AXI4 ports. That is why I am having confusion with how the DMA interacts with the hard processor.