Struggling with the (mSG)DMA Controller Core

Hi,

Sorry, I should have been more clear. I want to connect the DMA similarly to this configuration (which is for the Cyclone V): http://blog.reds.ch/?p=835 and add this configuration onto the GSRD I linked. I want to have the FPGA's DMA is connected to the hard processor of the Stratix 10 and then confirm the connection is correct by writing and reading data. The issue I am running into is that the (mSG)DMA require Avalon ports while the hard processor only has AXI4 ports. That is why I am having confusion with how the DMA interacts with the hard processor.