Stratix V Development board with QSFP ports

Hi Paul,

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but we don't know where to start.

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Start by reading about the transceiver toolkit and synthesizing a design using a Stratix V, eg., Altera's examples are here

http://www.altera.com/support/examples/on-chip-debugging/on-chip-debugging.html

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I don't have too much of knowledge of FPGAs but if anyone has knowledge of this or can point me in the right direction it would be much appreciated.

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Since you are new to FPGAs ... Under no circumstance download a design to your board until you understand what pin constraints are. If you do, you can potentially damage your (expensive) board!

My recommendation would be to also buy a lower-cost DE0-nano or BeMicro-CV and use that to learn the fundamentals of FPGAs.

While you are learning about FPGAs, you can post questions to this forum to ask for clarification on questions you may have.

Your FPGA design sequence should be;

1. Understand what it takes to blink an LED

2. Understand what it takes to blink an LED using Qsys, a programmable I/O pin, and JTAG

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

3. Understand what it takes to use the Transceiver Toolkit examples

I'm writing that tutorial now ... so hassle me when you want to read it :)

Cheers,

Dave

Thanks for the reply again Dave

I have a DE0-nano board also that I have been practicing with for some time. I understand the fundamentals of FPGAs and have no problem in blinking LEDs and doing other somewhat more complex stuff with VHDL or block diagrams.

Now that we have this S5-PCIe-HQ, it's a new world. :-) Our aim is to learn how to use it and eventually have it for transferring data at high rates. How to create a PCIe interface that we can understand and test , we have still not had any success. Now we wish to try and use the QSFP+ ports to read in data from one and transmit out the other. To get anything basic working right now would be an achievement. So far we can just blink the LEDs on the board.

It would be great if there was some step-by-step training for this board or FPGA that could eventually bring us up to a good level of understanding but I assume that they expect users of such boards to be already experts.

Yes, It would be great to read that tutorial :-) Thanks

Cheers,

Paul

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I have a DE0-nano board also that I have been practicing with for some time. I understand the fundamentals of FPGAs and have no problem in blinking LEDs and doing other somewhat more complex stuff with VHDL or block diagrams.

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Great!

Now, how about your understanding of Qsys? Do you know how to run a Modelsim simulation with an Avalon-MM master BFM?

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Now that we have this S5-PCIe-HQ, it's a new world. :-)

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Nah, its the same world, but your mistakes just get more expensive :)

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Our aim is to learn how to use it and eventually have it for transferring data at high rates. How to create a PCIe interface that we can understand and test , we have still not had any success. Now we wish to try and use the QSFP+ ports to read in data from one and transmit out the other. To get anything basic working right now would be an achievement. So far we can just blink the LEDs on the board.

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Did you try reading through the Transceiver Toolkit documentation?

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It would be great if there was some step-by-step training for this board or FPGA that could eventually bring us up to a good level of understanding but I assume that they expect users of such boards to be already experts.

Yes, It would be great to read that tutorial :-)

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Yep, I figured that :)

I'll work on it next week.

For now, take a look at the notes below on what I needed to do to get a Transceiver Toolkit design working with an Arria V. I'm pretty sure there is already a Stratix V design in the toolkit examples, so all you need to do, is to ensure that the top-level pin assignments for the transceiver are switched to those used on your board.

If you use a QSFP+ loopback or a QSFP+ direct attach copper cable that does not have redriver ICs, then you do not need to talk to the I2C controller in the QSFP+ cable to enable the lanes.

Cheers,

Dave

Hi Dave,

I just see your reply now.

I don't know how to run a Modelsim simulation with an Avalon-MM master BFM but would like to know.

I am just about to read your notes now on the Transceiver Toolkit design and thanks for that. If I use a QSFP+ loopback, do I need to link a cable between the two ports or can do it without?

Cheers,

Paul

Hi Paul,

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I don't know how to run a Modelsim simulation with an Avalon-MM master BFM but would like to know.

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Go through this tutorial;

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

This was written for an older version of Quartus, but the same general procedure works. Its written in SystemVerilog, since at the time, the Altera Verification IP Suite did not have good VHDL support. There is better support for VHDL now, however, I haven't used it, since simulation in SystemVerilog is ok with me (even though my synthesis code is in VHDL).

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If I use a QSFP+ loopback, do I need to link a cable between the two ports or can do it without?

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There's several loopback options;

1. A physical loopback connector that connects the TX and RX pins in the QSFP+ connector

http://www.elpeus.com/categories/qsfp-cables/qsfp-loopback-adapters.html

2. Internal loopback at the transmitter (nothing needed on the QSFP+ connector)

3. Internal loopback at the receiver (needs a QSFP+ cable between the transmitter and receiver)

Cheers,

Dave

Hi Dave,

I've been going through that tutorial and it helps alot.

The tutorial supplied test-bench on p.28 (Avalon-MM Master BFM) does not work however. When I try to compile using "vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

-L qsys_system_bfm_master" , I receive errors saying that could not find the package verbosity_pkg and avalon_mm_pkg.

The test-bench JTAG-to-Avalon-MM Master on P.29 works tho.

On p.31 under Synthesis and Simulation scripts it says to start Quartus and change to the Qsys BeMicro-SDK project and then use commands like "tcl> set TUTORIAL c:/temp/altera_jtag_to_avalon_mm_tutorial". How exactly do I do that in Quartus. Are those tcl commands?

I am having problems also understanding how to implement the host-to-FPGA communication from p.33. There doesn't seem to be a step-by-step guide on how it is done.

Thanks again for your help,

Paul

Hi Paul,

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The tutorial supplied test-bench on p.28 (Avalon-MM Master BFM) does not work however. When I try to compile using "vlog -sv $TUTORIAL/hdl/qsys_system/test/qsys_system_bfm_master_tb.sv

-L qsys_system_bfm_master" , I receive errors saying that could not find the package verbosity_pkg and avalon_mm_pkg.

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Yes, Altera has trouble keeping things consistent between tool versions. Take a look at the qsys_vip.zip in this thread:

http://www.alteraforum.com/forum/showthread.php?t=32952&page=3

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On p.31 under Synthesis and Simulation scripts it says to start Quartus and change to the Qsys BeMicro-SDK project and then use commands like "tcl> set TUTORIAL c:/temp/altera_jtag_to_avalon_mm_tutorial". How exactly do I do that in Quartus. Are those tcl commands?

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Yes, those are Tcl commands. If the Quartus Tcl console is not visible, you can access it via View->Utility Windows->Tcl console.

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I am having problems also understanding how to implement the host-to-FPGA communication from p.33. There doesn't seem to be a step-by-step guide on how it is done.

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"Its just software" :)

The step-by-step guide is to read the software, eg., the Tcl scripts.

Altera started with a tool called quartus_stp, but have moved their focus onto the System Console tool.

Download the bemicro_cv_examples.zip file from this thread (the version from post# 5)

http://www.alteraforum.com/forum/showthread.php?t=43992

and look in the ddr/scripts folder at jtag_cmds.tcl. All you really need to understand is; open/close and read/write.

Cheers,

Dave

Hi Dave,

When I send the command from page 31 : "source scripts/synth.tcl" , I receive the error: "error: can't find package ::quartus:: project while executing package require ::quartus:: project"(file "scripts/synth.tcl" line 45) while executing..".

Do you know what the issue is?

Also, when I get to the point of communicating with the board from the the host, If I write a value to RAM for example, how can I confirm that the value is there? Can I also use pin planner to assign the LED ports to the pins on my DE0-Nano board and then observe them changing when I send tcl commands (after re-compiling and programming the board of course) ?

Thanks,

Paul

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When I send the command from page 31 : "source scripts/synth.tcl" , I receive the error: "error: can't find package ::quartus:: project while executing package require ::quartus:: project"(file "scripts/synth.tcl" line 45) while executing..".

Do you know what the issue is?

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So long as you are sourcing that script from the Quartus II Tcl console, it should work fine.

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Also, when I get to the point of communicating with the board from the the host, If I write a value to RAM for example, how can I confirm that the value is there?

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Read it back :)

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Can I also use pin planner to assign the LED ports to the pins on my DE0-Nano board and then observe them changing when I send tcl commands (after re-compiling and programming the board of course) ?

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Sure, if you make sure the pin planner assignments are correct for your hardware, then you can rebuild the design for your specific hardware.

Cheers,

Dave

I have sourced the tcl file "..\hdl\boards\bemicro_sdk\share\scripts\jtag_cmds_sc.tcl" but when I then try to change the LED values with command "led write 0x23" for example, nothing happens. I assume that that tcl commands script is specifically for the bemicro board.

If that is just the issue, where can I get one that suits the DE0-nano board? I am not a pro at tcl so unable to create my own.

Cheers,

Paul