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Honored ContributorStratix IV GX Pin Assignment
Hi,
I'm working on the Stratix IV GX 230 board and I'm trying to use the Triple Speed Ethernet in RGMII mode with MDIO. I did everything well untill the moment I needed the PIN in order to connect the MAC with the PHY. But I couldn't find any information concerning the following pin: For the MDIO: -mdio_oen -mdio_in -mdio_out -mdc For the RGMII: -tx_control_to_the_triple_speed_ethernet_0 -rx_controle_from_the_triple_speed_ethernet_0 -tx_clk_from_the_triple_speed_ethernet_0 -rx_clk_from_the_triple_speed_ethernet_0 -rgmii_in_from_the_triple_speed_ethernet_0 -rgmii_out_to_the_triple_speed_ethernet_0 All I could find was the PHY PIN assignment for the SGMII with LVDS transceiver there: http://www.altera.com/literature/manual/rm_sivgx_fpga_dev_board.pdf And even the documentation about the bank of IO couldn't tell more about that. Have anyone ever managed to use the RGMII with the Stratix IV in order to have an Ethernet output? Thank you. Michel28 Replies
Altera_ForumFrom what I see you can only use the Marvel PHY on this board in SGMII mode and not RGMII.
As for the MDIO pins, connect mdc to ENET_MDC and make a small tristate output for ENET_MDIO: when mdio_oen is 0 it should be an output with the value mdio_out, and when mdio_oen is 1 it should be an input, and the value fed to mdio_in.- Altera_Forum
Thank you for your answer Daixiwen.
As you said I used the SGMII mode for the TSE and I connected the PIN as indicated in the User Guide. I also connected MDC and MDIO (tristate) with the PIN that were indicated by the same User Guide. Then I ran the Simple Socket Server in both RGMII and normal mode (the samples that are given in Eclipse Nios 2) with the DHCP unused but it seems that there is still no PHY detected in the design. And whenever I try to use telnet to the board with telnet I get no answer. This is strange because even if there is no PHY, the SSS says that it's listening on port 30 with an Error: No PHY detected. I've seen that other people had this problem before but I still don't see any answer to my problem. Has anyone find the solution to this problem? Thank you in advance. - Altera_Forum
No PHY detected seem to indicate that the MDIO interface isn't working. How did you make the tristate buffer for the MDIO data signal?
Put some Signaltap probes on MDC, the 3 MDIO signals from the TSE, and the tristated MDIO pin to check that it is working properly and that you get an answer from the PHY. - Altera_Forum
I'm making my tristate MDIO data signal like that :
-- the_tse_0 ref_clk_to_the_triple_speed_ethernet_0 => system_clk, rx_recovclkout_from_the_triple_speed_ethernet_0 => rx_recovclkout, rxp_to_the_triple_speed_ethernet_0 => rxp, txp_from_the_triple_speed_ethernet_0 => txp, mdc_from_the_triple_speed_ethernet_0 => mdc, mdio_in_to_the_triple_speed_ethernet_0 => mdio_inout, mdio_oen_from_the_triple_speed_ethernet_0 => system_mdio_oen, mdio_out_from_the_triple_speed_ethernet_0 => system_mdio_out ); mdio_inout <= system_mdio_out when (system_mdio_oen = '0') else 'Z' when (rising_edge(clk)); And I've put some probes on the signal you said but everytime that I try to read these signal, I get : -a clk signal on mdc and mdc_out_from_the_triple_speed_ethernet -'1' in mdio_inout mdio_in mdio_oen and mdio_out signal. My trigger condition is a falling edge of mdio_oen. According to my equation, this is right but is it normal to see mdio_in and mdio_oen mdio_out '1' at the same time? - Altera_Forum
Does mdio_oen always stay at 1? That's strange, it should go to 0 when the TSE wants to read the PHY's answer. You should also se some toggling on mdio_out and the mdio pin.
I'm not sure how Quartus will understand and synthesize this:
but it probably won't be what you expect. Just ule a regular buffer:mdio_inout <= system_mdio_out when (system_mdio_oen = '0') else 'Z' when (rising_edge(clk));
No need to take the clock into account here.mdio_inout <= system_mdio_out when (system_mdio_oen = '0') else 'Z'; - Altera_Forum
Thanks for your help Daixiwen, I have already changed the buffer to what you said (because it had a strange behavior before) and my mdio_oen goes 0 when he wants the PHY's answer and 1 otherwise.
I can also see some toggling on the mdio_out pin which I believe is reassuring.. I'm compiling the project and I'll see if my PHY will finally work after that. - Altera_Forum
Well I have done all of this my MDIO_inout is correctly following my MDIO_out and my MDIO_in is following my MDIO_inout with a MDC frequency of 2MHz.
And still, it seems that my PHY isn't detected by my iniche_init.c process. I still have the: prepped 1 interface, initializing... [tse_mac_init] Then nothing. My design is composed of the Nios II connected to a TSE via two SGDMA and an on_chip_mem. The TSE is configured with SGMII, MDIO, SGMII Bridge enabled, and I have connected the TSE output pin to: mdc -> PIN_AH34 mdio_inout -> PIN_M33 txp -> PIN_L29 rxp -> PIN_AC31 I'm quite sure that the tri state bus is working fine with the signaltap. And the software I'm loading into the Nios II is a Simple Socket Server configured without the DHCP. I have already tried to use the TSE in GMII, RGMII mode. Does anyone knows what I could try to do in order to make this Triple Speed Ethernet output work? Thank you by advance. Michel - Altera_Forum
Do you see the PHY's answer on the MDIO pin? i.e. is there any time with the mdio pin or mdio_in different than 1 when mdio_oen is 1?
- Altera_Forum
I have no answer coming from the PHY when the MIDO_oen = '1'.
The signal mdio_out mdio_in and mdio are changing only when the mdio_oen = '0'. Does that mean that my transceiver isn't working well? I use a LVDS transceiver configured by the Triple Speed Internet. I haven't changed the default setting for this component. - Altera_Forum
It's strange because I just found a documentation which says that it's actually possible to instanciate RGMII with the Stratix IV GX.
http://www.altera.com/literature/manual/rm_siv_gx_si_devkit_board.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=stratix%20iv%20gx%20mdio Still it says that the PIN for the RXP is D31 instead of this document: http://apegate.roma1.infn.it/~ammendola/altera/s4gx_pcie_b.pdf In which we can see that the RXP pin is the AC31. Which of these document should I use in order to link my rxp, txp, mdio, mdc finally?
