Stratix IV GX Pin Assignment

I'm making my tristate MDIO data signal like that :

-- the_tse_0

ref_clk_to_the_triple_speed_ethernet_0 => system_clk,

rx_recovclkout_from_the_triple_speed_ethernet_0 => rx_recovclkout,

rxp_to_the_triple_speed_ethernet_0 => rxp,

txp_from_the_triple_speed_ethernet_0 => txp,

mdc_from_the_triple_speed_ethernet_0 => mdc,

mdio_in_to_the_triple_speed_ethernet_0 => mdio_inout,

mdio_oen_from_the_triple_speed_ethernet_0 => system_mdio_oen,

mdio_out_from_the_triple_speed_ethernet_0 => system_mdio_out

);

mdio_inout <= system_mdio_out when (system_mdio_oen = '0')

else 'Z' when (rising_edge(clk));

And I've put some probes on the signal you said but everytime that I try to read these signal, I get :

-a clk signal on mdc and mdc_out_from_the_triple_speed_ethernet

-'1' in mdio_inout mdio_in mdio_oen and mdio_out signal.

My trigger condition is a falling edge of mdio_oen.

According to my equation, this is right but is it normal to see mdio_in and mdio_oen mdio_out '1' at the same time?