n_nuti
New Contributor
2 years agoStratix 10 H-TILE Signal Integrity Kit - PCIE
Hello,
My team and I are trying to use an FMC to PCIE adapter on an S10 h-tile signal integrity kit. In doing so, I need to use the following pins to connect to the H-TILE PCIE IP:
I'm currently using AE14, and using this pin causes the following to happen during programming:
I read from this page that it's caused from the 3V0 lanes (VCCH and VCCRR/L):
https://www.intel.com/content/www/us/en/support/programmable/articles/000074933.html
I'm trying to look at the schematics to understand what else is required for this to work. Can you please suggest any changes to stop this configuration error from happening?
Thank you,
Nick