S10 UART1 Control

Hello aikeu,

Thanks for replying!

Firstly, I am pretty sure I enable the HPS UART 1 in your qsys in Platform designer.

Then I am trying to use U-Boot as the Secure Monitor (non-ATF way) to control UART1 on L4 Slave Peripheral BusI, so the way I do is to use the pre-built sdimage downloaded online, which contains four files in FAT32 such as "Image", "u-boot-dtb.img", "u-boot.scr", "socfpga_stratix10_socdk.dtb". I keep "Image" and "u-boot-dtb.img" the same as before. I change "u-boot.scr" with adding l4_sp register (mw.l 0xFFD21070 0x01010101) configuration to enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu, dma) to UART1. Also I update "socfpga_stratix10_socdk.dtb" with UART1's status changing from "disable" to "okay".

However, what I have done does not make UART1 output something which the output data is always in loop of UART1 register (0xFFC02114).

Could you please give me some advice about my situation?

Thanks.

Regards,

Stanley

Hello aikeu,

I am sorry I forget to renew my comment. I try to add those two items in my socfpga_stratix10_defconfig but it still does not work.

However, I have something new which I open another community https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/How-to-Read-Write-L4-Peripheral-Slave-Bus-on-S10-SX-Device/td-p/1364632.

This new community shows more information about my problem. Could you please check this new community and if you have any suggestions please let me know.

Best Regards,

Hans_1st