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Hans_1st's avatar
Hans_1st
Icon for New Contributor rankNew Contributor
4 years ago

S10 UART1 Control

Hello, I am using Stratix 10 SX Development Kit and I want to control UART1 output something by using HPS. How many and what kind of registers should I configure like l4_sp register for Cyclone V ...
aikeu's avatar
aikeu
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi stanley015,

Have you enabled the HPS UART 1 in your qsys in Platform designer?

Then consider the changes to add UART1 in the device tree when building your U-boot. By default, UART0 is already enabled and it's default settings can be seen in the device tree configuration for reference.

Thanks.

Regards,

Aik Eu

  • Hans_1st's avatar
    Hans_1st
    Icon for New Contributor rankNew Contributor
    4 years ago

    Hello aikeu,

    Thanks for replying!

    Firstly, I am pretty sure I enable the HPS UART 1 in your qsys in Platform designer.

    Then I am trying to use U-Boot as the Secure Monitor (non-ATF way) to control UART1 on L4 Slave Peripheral BusI, so the way I do is to use the pre-built sdimage downloaded online, which contains four files in FAT32 such as "Image", "u-boot-dtb.img", "u-boot.scr", "socfpga_stratix10_socdk.dtb". I keep "Image" and "u-boot-dtb.img" the same as before. I change "u-boot.scr" with adding l4_sp register (mw.l 0xFFD21070 0x01010101) configuration to enable both secure and non-secure transactions for all masters (axi_ap, F2H, mpu, dma) to UART1. Also I update "socfpga_stratix10_socdk.dtb" with UART1's status changing from "disable" to "okay".

    However, what I have done does not make UART1 output something which the output data is always in loop of UART1 register (0xFFC02114).

    Could you please give me some advice about my situation?

    Thanks.

    Regards,

    Stanley