S10-DX-Kit PCIe driver failure

Hi Sir,

Please try the command sudo ./install instead of ./install.

Also, what quartus version that you use? I acknowledge there are some issue in 19.4, thus please try with 19.3 or 20.1.

you can see the issue discussion here. they can use the design successfully if using 19.3.

I am using SOF file which came with SW package. I am running install command as root user.

the problem was that recent version of kernels uses different arguments for access_ok function.

- access_ok(type, addr, size)

+ access_ok(addr, size)

i made these changes in driver files supplied with the SW package, and i was able to compile the driver. However when running test application DMA tests (option 9) failed; and performing link test-100 rds/wrs (option 0 ) hung/crashed my system. can you help ?

thanks

Hi Sir,

I am not aware about any pre-compile sof that came with SW package. By right, you should generate the example design using quartus (as mentioned by the User Guide), then compile the design to generate the SOF.

To make the DMA run successfully, you should not use Quartus 19.4. Seem like the issue that you are facing is matching with this KDB.

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2020/why-does-the-data-transfer-test-is-hang-when-running-intel--fpga.html

Regards

Boon Chiek

i got the installer package from kit`s web page https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-s10-dx.html

"ES" in screenshot above is hyper link to a zip file.

once you extract the zip file this path has a sof file -stratix-10-dx-1sd280pt2f55-fpga-rev-a--v19.3b222-v1.0\stratix10DX_1sd280pt2f55_fpga_revA_v19.3b222_v1.0\examples\pcie_ed\pcie_ed.sof

i loaded this sof file, the same location also have a zip file with SW package; I am using same SW/driver which is supplied.

Hi Sir,

Please try the sof as attached in this thread - https://forums.intel.com/s/question/0D70P000006hLBZ/system-hangs-while-testing-intel-fpga-ptile-avalon-memory-mapped-avalonmm-ip-for-pci-express-design-example-user-guide-example-design

This sof is verified work at our side and also the customer side.

i have another question

in attached screenshot-

i tried option 3 & 4 to interact with config space

> i attempted writing value 0xa00 at address 0x100; and as per screenshot it was successful.

> i attempted to read address 0x100h after above step; and it returned 0x14820001

> if write was successful why its reading wrong value back and not the value i had just written?

can you find me address range in this design where i can write and read same values back?

Hi Sir,

By right user should not change the value of these register.

I checked Table 109. PCIe Configuration Space Registers for x16/x8/x4 Controllers

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ptile_pcie_avst.pdf#page=174

For address 0x100, it is Advanced Error Reporting (AER), and according to PCIe spec, these register is RO only (see screenshot as below).

So, write will not takes effect.

If you really want to write into these register, you may check PCIe spec which register attributes is RWs. Furthermore, if you simply change the register value might cause the system to crash.

Lastly, for new question, it is better if you can create a new thread. this is to ease conversation tracking and ease for other user to search related topic.