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New Contributor

5 years ago

Solved

Reference clock for PLL

Dear,

In Arria 10 Datasheet, the max frequency of three PLL (CMU, ATX, fPLL) is 800MHz (Page 28).

However, in a10gx_si_e4 schematic, I found that Y6 oscillator (Si570) was programed to 875MHz.

Is this OK?

EngWei_O_Intel
5 years ago
Hi Yang Ni

The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.

For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.

Thanks.

Eng Wei

8 Replies

EngWei_O_Intel
Frequent Contributor
5 years ago
Hi Yang Ni

Thanks for your inquiry. Can you share the link of a10gx_si_e4 schematic?

Thanks.

Eng Wei
- Fresh_Leon
  New Contributor
  5 years ago
  Dear, Wei
  
  https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/arria10/signal-integrity-dev-kit/arria10GX_10ax115sf45_si_v15.1.zip
  
  Schematic are in zip file. After you un-zip it, the schematic should be in following path.
  
  "arria10GX_10ax115sf45_si_v15.1\board_design_files\arria10_10ax115s2f45i2sg\schematic"
  
  Brs,
  
  Leon
  - EngWei_O_Intel
    Frequent Contributor
    5 years ago
    Hi Yang Ni
    
    I still need some time to check with the board team before getting back to you.
    
    Thanks.
    
    Eng Wei