Forum Discussion
New ContributorReference clock for PLL
Hi Yang Ni
The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.
For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.
Thanks.
Eng Wei
New ContributorDear, Wei
Schematic are in zip file. After you un-zip it, the schematic should be in following path.
"arria10GX_10ax115sf45_si_v15.1\board_design_files\arria10_10ax115s2f45i2sg\schematic"
Brs,
Leon
Frequent ContributorHi Yang Ni
I still need some time to check with the board team before getting back to you.
Thanks.
Eng Wei
- Fresh_Leon
It's OK.
Take your time.
Brs,
Leon
- EngWei_O_Intel
Hi Yang Ni
The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.
For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.
Thanks.
Eng Wei
- Fresh_Leon
Hi, Wei
Understood.
Thanks.
Brs,
Leon
