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Fresh_Leon's avatar
Fresh_Leon
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5 years ago
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Reference clock for PLL

Dear, In Arria 10 Datasheet, the max frequency of three PLL (CMU, ATX, fPLL) is 800MHz (Page 28). However, in a10gx_si_e4 schematic, I found that Y6 oscillator (Si570) was programed to 875MHz. ...
  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    5 years ago

    Hi Yang Ni

    The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.

    For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.

    Thanks.

    Eng Wei