Forum Discussion
Reference clock for PLL
- 5 years ago
Hi Yang Ni
The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.
For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.
Thanks.
Eng Wei
It's OK.
Take your time.
Brs,
Leon
Hi Yang Ni
The feedback I got is that we have to follow the latest datasheet, handbook, and pin connection guideline for new board designs.
For the existing board we are using, it depends on how the Quartus/IP rule checks, if the reference designs are based on an older Quartus tools which allowed 875MHz, then we can use as it is. If we upgrading the reference design and encounter the error, we have to change both RTL design and program the oscillator as well.
Thanks.
Eng Wei
- Fresh_Leon5 years ago
New Contributor
Hi, Wei
Understood.
Thanks.
Brs,
Leon
- EngWei_O_Intel5 years ago
Frequent Contributor
Cool Leon. I will transition this case to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you for contacting us.
Eng Wei
- EngWei_O_Intel5 years ago
Frequent Contributor
Hi Leon
You can set this case to closure too if there is no further request needed on this case.
Thanks.
Eng Wei