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PedroJServian's avatar
PedroJServian
Icon for New Contributor rankNew Contributor
10 months ago

Problems with DEV_CLRN and PINs, MAX10

Hi colleagues, I have been dealing with a problem with a design I have made for my 10M08 FPGA. My program have a "PWM treatment" design that gets some PWM signals from a microcontroller and makes a ...
Board Debug
Fpga Devkit
FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
10 months ago

When DEV_CLRn isn't used in your design, you should disable global device clear function in Device & Pin settings. If you already did, your issues can't be related to DEV_CLRn level.

Problems at startup may be caused by weak-pullup of FPGA IO pins in unconfigured state that cause a high level during start-up if no external pull-down resistors of sufficient strength are connected.