PC <-> S530Dev. Bd. Reg R/W interface?

8-}

(lengthening to > 10 char)

hi!

it seems that i have a similar problem like yours.

i wanna read and write register of my nios system by using the jtag to avalon master bridge by using system-console.

i can do it by using the system-console.exe.

my problem is, that i wanna use the new (quartus 2 11.0) Matlabapi to do this.

wombat - altera guru - also gave me some hints how i can do it (last page http://www.alteraforum.com/forum/showthread.php?t=28699). but i get the error:

Could not initialize class com.altera.systemconsole.internal.plugin.jtag.aji.AJICable

it seems like a problem with the jtagdni.dll but i don´t know how i can fix it.

perhaps you can give me an idea how to fix it ...

greets

basti-b - I would post this in a new thread - you'll get greater visiblity. thanks!

/j

Hi Dave - it's been a busy few days.

I got my board up, ran all the system tests. did the Qsys example, downloaded to the board, and saw that working. Played with System Console and the 'dashboard'. And now I'm trying to push my own project through the process. What I'm finding is a disconnect between Qsys and Quartus. I mean, after I have a project complete in Qsys, how do I get it into an FPGA? Do I set up the project, pinout, etc, manually, or is there some Qsys-> Quartus tool that helps. I'd be surprised if there wasn't, but I'm not finding it. I appear to have to generate project file, sdc file, etc, from scratch. Really?

Thanks!

/j

--- Quote Start ---

What I'm finding is a disconnect between Qsys and Quartus. I mean, after I have a project complete in Qsys, how do I get it into an FPGA? Do I set up the project, pinout, etc, manually, or is there some Qsys-> Quartus tool that helps. I'd be surprised if there wasn't, but I'm not finding it. I appear to have to generate project file, sdc file, etc, from scratch. Really?

--- Quote End ---

Qsys generates a component. There's nothing special about that component, it just happens to be automatically generated.

An FPGA design consists of a pinout, SDC file, and HDL files; one or more of which may be Qsys generated components.

I typically generate top-level designs using;

* a generic top-level design entity (VHDL) containing all pins on the board

* a pin assignments Tcl script that sets up all the I/O

* SDC files

* A design-specific Tcl script that ties it all together (runs the Quartus build)

The top-level entity/architecture file is copied-and-pasted into each design, and then the architecture body is edited to connect the design-specific top-level design into the generic top-level design (which always has the same pin names). For example, lets say I have a Qsys component called qsys_test that I want to simply drop into the FPGA. I would take my Stratix IV GX development kit top-level design s4gxdk.vhd and inside that file instantiate u1 as the qsys_test component, then connect up whatever pins I need, eg., connect a qsys_test bus called pio(7 downto 0) to the LEDs or a GPIO bus in the top-level generic design.

So, there is a little manual work required, but its similar between designs, so most of it can use common scripts (to minimize copying files), or a common template that can be copied-and-pasted, followed by minor editing.

Cheers,

Dave

Thanks Dave - I assume the scripts you refer to are your own. I admit I'm dealing with it by starting with the .qsf from the development kit and working from there. The examples/tutorials gloss over the top-level build so I was hopeful there was some magic there 8-}

thanks!

/j

Hi Dave - I'm getting close to banging my head against the wall now. but see the next posting..

/j

So let me be more specific: I have assembled a project in Qsys consisting of a Clock source, a JTAG-to-Avalon Master Bridge, and a custom Avalon Slave which is no more than a register file. I used Qsys to connect the reset network*, and generate all the files, and instantiated the top-level file from Qsys as my top-level project file. There are only 2 inputs (clk, reset_n), for which I correctly connected pins (based on the example project for my FPGA board). I also constrained the clock, and used the my_constraints from the example project to constrain the JTAG interface. I then built it. The warning count was very low and the warnings seemed reasonable. I then programmed the board. (with the rotary switch on "0"). I then brought up system console.

These commands work

set mm [lindex [get service paths master] 0]

open_service master $mm

is_service_open master $mm // returns 1

However - any other commands, like

jtag_debug_sample_clock $mm

jtag_debug_sample_reset $mm

jtag_debug_loop $mm <number>

jtag_debug_sense_clock $mm

or, the one I want

master_write_32 $mm 0x0 0x1

All produce a message "channel closed". The jtag sense/sample commands all return "0", and the jtag_debug_loop returns "error: java.lang.NullPointerException while executing <cmd>".

The master_write_32 returns "error: java.lang.RuntimeException: Channel closed while executing <cmd>'"

I feel like I'm awfully close here, and just haven't tagged second. What does "Channel closed" mean????

Thanks!

/j

*I really think Qsys didn't do the reset network right - it tied everything to everything. So I tried it again with a daisy chain - clk source -> JTAG/Avalon Master -> my Slave. didn't make a different but this seems more correct.

Its quite possible you have a design error.

Did you try running the design in Modelsim first?

The Verification IP suite contains an Avalon-MM Master BFM that can be added to your Qsys design. You can use that component to generate Avalon-MM master read/write transactions.

Cheers,

Dave

That's my next step, I wish I knew what the error meant though.

Dave - let me ask you something. All I'm really interested in is adding the JTAG-To-avalon-master to my designs. Now that I've been through Qsys, and, as you say, Qsys is just a way to generate RTL, do I really need all the overhead? Why can't I just create my own RTL with a call to the JTAG-To-avalon-master, + my code, and use a QIP file so Quartus can find the avalon component. It seems much easier...

Thanks!

/j