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Altera_Forum
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15 years ago

PC <-> S530Dev. Bd. Reg R/W interface?

Hi - so I just got my first Altera Development kit (S-IV GX S530). My "hello world" project starts with a tiny user-designed design (i.e. RTL code) that I download to the board that consists of so...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Its quite possible you have a design error.

Did you try running the design in Modelsim first?

The Verification IP suite contains an Avalon-MM Master BFM that can be added to your Qsys design. You can use that component to generate Avalon-MM master read/write transactions.

Cheers,

Dave