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Altera_Forum
Honored Contributor
Honored ContributorPartial Reconfiguration in DE2
Greetings!
I posted a while back about a digital image processing platform that demonstrates a jpeg compression algorithm to process the image. The JPEG encoding is an option that a user can apply to their images taken by a CMOS camera that came with the DE2 development board. I got plenty of help from the community in determining the following: 1. Implement a controller using NIOSII to service user interface commands (eg. capture, save, compress) 2. That same NIOSII controller will also serve as a reconfiguration device to reconfigure the image processing part of the system - the block that implements the JPEG compression. 3. That block needs to be reconfigured because besides the assumption that the Logic Elements that the JPEG module will occupy will overwhelm the 33,000 LEs the FPGA chip in the DE2 can accommodate, new algorithms such as BMP compression, etc. may be made in future developments. (This is a platform after all). 4. daniel.kho suggested the use of a scan chain to load the bitstream of a new algorithm to reconfigure the processing block. He stated that I don't have to reconfigure the whole system. My concerns now are: 1. The cyclone II device does not support partial reconfiguration according to Altera http://www.altera.com/support/kdb/solutions/rd11192009_959.html 2. If this is so, then how do i implement the reconfiguration of a certain part of the fgpa chip using the scan chain? Does the scan chain fall under the partial reconfiguration? 3. daniel.kho also stated that I won't be loading an SOF/POF file into the FGPA to reconfigure with just a new compression algorithm like BMP during run time. so what would i be loading? Basically, daniel.kho helped me in making this conclusion before: I will load the system into the FPGA using QuartusII. The system involves the reconfiguration controller that is a scan chain. After that Quartus can be disconneted totally and when a new algorithm is developed, it will be accessed in a memory (SD card) and this bitstream will be scanned by the scan chain to reconfigure the processing block. The system is now configured with the new compression algorithm. Can this be done in the Cyclone II? Thank you in advance.18 Replies
Altera_ForumIt's not to me clear, what your exactly asking for. No Altera FPGA supports partial reconfiguaration up to now. Altera has has announced it as a feature to come, see Altera.com.
In so far it's clear, that total reconfiguration is the only option at present. What do you want to achieve with Cyclone II? Use it as a reconfiguration controller or is it the device to be reconfigured?- Altera_Forum
I see, so the Stratix V that will support the partial reconfiguration is not yet in the market. Okay, thanks.
--- Quote Start --- In so far it's clear, that total reconfiguration is the only option at present. What do you want to achieve with Cyclone II? Use it as a reconfiguration controller or is it the device to be reconfigured? --- Quote End --- Well, I only have one board and one Cyclone II and the system needs an FPGA implementation (HDL) of JPEG compression that will compress image data and controller for the user interface, peripherals and memory that is implemented in NIOSII + Avalon Bus. There are 2 problems encoutnered: 1. The Cyclone II of the DE2 board only has 33,000 LEs available and the JPEG implementation we have compiled to 45,000 LEs. (Not including the NIOSII controller, interfaces to peripherals) 2. Since the system is an image processing platform, JPEG compression will not be the only algorithm used therefore if the user wanted to use another algorithm say bmp compression then the JPEG compression should be replaced by bmp compression at run time. This means that the NIOSII controller + interfaces + memory modules will not be changed, only the compression block. This is why partial reconfiguration was discussed, but since it is not yet a feature in Altera devices, I need a way to implement this. I am considering the following: 1. PC to DE2 Board interface: A software will configure the whole FGPA everytime a different compression is chosen 2. Scan chain: as suggested by daniel.kho, implement a scan chain that will load the bit stream to a part of the FGPA to change the configuration of that part. is this considered as partial, if yes, can it be done? 3. Use 2 boards: 1 for the controller, 1 for the image processing. basically, what other ways are there in doing this kind of system? I hope I was able to make it clearer :) Thank you for your help. - Altera_Forum
Additional:
First it is the device to be reconfigured because of the image compression part. Second, if no PC interface will be done, then it is also the reconfiguring device. Thanks :) - Altera_Forum
Unfortunately, I'm not able to refer the suggestion of daniel.kho to a documented Altera FPGA feature. If the scan chain used for JTAG device configuration would effectively allow a partial (re)configuration, it's at least undocumented. I wonder, how you should be able to use it?
- Altera_Forum
I see... Well, if that's the case, that its undocumented, how can I implement my system without using partial reconfiguration then?
What would be my best bet? Thank you. - Altera_Forum
Altera provides the remote update Megafunction, that allows to choose between multiple configuration images from a flash memory. Unfortunately, it's not supported for Cyclone II. With Cyclone II, an external configuration controller (e.g. MAX II) would be required for a similar functionality. But I don't think, that it's possible with the existing DE2 hardware.
- Altera_Forum
Okay, so the system I want to implement can't be done in the DE2?
How about if I interface the board to my PC and control it from there, and make a software that will change the configuration of the FPGA chip without using the programmer in Quartus? Thank you. - Altera_Forum
Hi Mark, sorry I can't find back the original post. So I'll post here instead.
The idea of having partial reconfiguration on any FPGA device is actually to simply design your own "soft" Partial Reconfiguration Block... or whatever you'd like to call it. It is something like having the whole scan chain designed yourself, instead of using Altera's partial reconfiguration hard circuitry on silicon. Only some devices support it, as FvM mentioned. I personally do not know the details of this new partial reconfiguration feature that Altera is offering. But what I know is, there are people who designed their own "soft" reconfiguration circuitry to "program" or "change some settings" of some parts of their design. So, if you would like to have parts of your circuit change to a different user setting, you can design an interface that hooks up to your own Partial Reconfiguration Block. The interface can be any interface - RS232, USB, Ethernet, whatever... but the idea is to use the interface to send your user configuration data into your scan chain (this is your own Partial Reconfig Block). The partial reconfig block design should be as simple as having some logic to shift the data stream (from the interface) to some registers, or internal memory blocks. You can then have logic to read from this memory (or registers) and decide how the other parts of your design should behave (depending on the settings stored in memory). Hope this helps, Daniel - Altera_Forum
Hi Mark,
To make things clearer, the "scan chain" you mentioned in your earlier posts refers to the JTAG chain, while the one I was referring to (dubbed "soft" Partial Reconfiguration Block - designed yourself) does not refer to the JTAG chain. This of course, has to be a separate interface from the JTAG interface, and you can use any standard interfaces like RS232, USB, etc. or even use your own non-standard interface with your own header. Hope this explanation is clear for you. Regards, Daniel - Altera_Forum
Sorry this had to come in multiple posts.
But well, after more reading, I came to the conclusion that you're getting the idea... well, almost! --- Quote Start --- How about if I interface the board to my PC and control it from there, and make a software that will change the configuration of the FPGA chip without using the programmer in Quartus? --- Quote End --- Oh yes, this is the whole point... your software that you make would have to communicate with said interface (RS232, USB, etc.). Your software would send your user configuration data (new settings) via this interface to your FPGA. Then, your "soft" Partial Reconfiguration Block receives these new settings and stores them in memory. After that, you have some custom logic that reads from this memory and decides how your other blocks would behave based on these new settings! Well, you don't need the JTAG port anymore after you've configured the FPGA the first time... you only need the said interface that connects to your PC (and of course, you can unplug it if you don't need to send new settings). Anyway, using the PC is just one example... this can be any other circuit board, or chip, etc. that sends the settings... Btw, well done...brava! Regards, Daniel
