Partial Reconfiguration in DE2

Hi Mark, sorry I can't find back the original post. So I'll post here instead.

The idea of having partial reconfiguration on any FPGA device is actually to simply design your own "soft" Partial Reconfiguration Block... or whatever you'd like to call it. It is something like having the whole scan chain designed yourself, instead of using Altera's partial reconfiguration hard circuitry on silicon. Only some devices support it, as FvM mentioned.

I personally do not know the details of this new partial reconfiguration feature that Altera is offering. But what I know is, there are people who designed their own "soft" reconfiguration circuitry to "program" or "change some settings" of some parts of their design.

So, if you would like to have parts of your circuit change to a different user setting, you can design an interface that hooks up to your own Partial Reconfiguration Block. The interface can be any interface - RS232, USB, Ethernet, whatever... but the idea is to use the interface to send your user configuration data into your scan chain (this is your own Partial Reconfig Block).

The partial reconfig block design should be as simple as having some logic to shift the data stream (from the interface) to some registers, or internal memory blocks. You can then have logic to read from this memory (or registers) and decide how the other parts of your design should behave (depending on the settings stored in memory).

Hope this helps,

Daniel