Forum Discussion
On board 2 bit input
Hello, I have the MAX 10 DE-LITE board and im trying to create for example a simple mux on a hardware level so i can run it on the board. So after creating a GOLDEN TOP sv file my problem is how can i call my module with the correct on pin boards?
This is my module
So on the GOLDEN TOP sv file how can i call it?
Task2 try1(MAX10_CLK1_50,ARDUINO_IO[9]_ARDUINO_IO[8],ARDUINO_IO[7]);
Basically my input for the sel [1:0] is arduino_io [9] and arduino_io[8].
I found how to do it on the pin planner but im just curious to see how it works there.
Thanks in advance
Hi,
The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.
Have to change to packed array input logic [1:0] sel,
Thanks,
Best Regards,
Sheng
7 Replies
- ShengN_altera
Super Contributor
Hi,
The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.
Have to change to packed array input logic [1:0] sel,
Thanks,
Best Regards,
Sheng
- sstrell
Super Contributor
Ah, missed that!
- sstrell
Super Contributor
Need to see your top-level code, but a correct instantiation would be something like:
Task2 try1 (MAX10_CLK1_50,{ARDUINO_IO[9],ARDUINO_IO[8]},ARDUINO_IO[7]);
Curly brackets are concatenation.
Also note that initial blocks are not synthesizable. You should have a reset control signal and use that to reset all those counters.
- antonto
Occasional Contributor
Thank you for your time.
Im getting this error
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match
and this one
Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type
Same with the answer from Sheng
- ShengN_altera
Super Contributor
Hi,
Or like below also get same result
Task2 try1 (
.clk50(MAX10_CLK1_50), .sel({ARDUINO_IO[9], ARDUINO_IO[8]}), .y(ARDUINO_IO[7])
);
Thanks,
Best Regards,
Sheng
- antonto
Occasional Contributor
Thank you for your time.
Im getting this error
Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match
and this one
Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type
Same with the other answer from Sstrell- sstrell
Super Contributor
You would need to show your top-level code to understand why the I/O is not matching the sel data type.