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antonto's avatar
antonto
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

On board 2 bit input

Hello, I have the MAX 10 DE-LITE board and im trying to create for example a simple mux on a hardware level so i can run it on the board. So after creating a GOLDEN TOP sv file my problem is how can...
Board Debug
  • ShengN_altera's avatar
    ShengN_altera
    2 years ago

    Hi,


    The error occurs because of this line input logic sel [1:0], in Task2 module due to unpacked array.

    Have to change to packed array input logic [1:0] sel,


    Thanks,

    Best Regards,

    Sheng


sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
2 years ago

Need to see your top-level code, but a correct instantiation would be something like:

Task2 try1 (MAX10_CLK1_50,{ARDUINO_IO[9],ARDUINO_IO[8]},ARDUINO_IO[7]);

Curly brackets are concatenation.

Also note that initial blocks are not synthesizable. You should have a reset control signal and use that to reset all those counters.

  • antonto's avatar
    antonto
    Icon for Occasional Contributor rankOccasional Contributor
    2 years ago

    Thank you for your time.

    Im getting this error
    Error (10928): SystemVerilog error at DE10_LITE_Golden_Top.v(136): packed array type cannot be assigned to unpacked array type - types do not match

    and this one

    Error (10716): SystemVerilog error at DE10_LITE_Golden_Top.v(136): can't pass value from actual to formal input "sel" with incompatible type

    Same with the answer from Sheng