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ymiler's avatar
ymiler
Icon for Contributor rankContributor
1 year ago
Solved

ODDR clock

Hi,

I need to create a source synchronous connection between two FPGAs.

FPGA A needs to transmit 32 data bits with a clock to FPGA B.

All 32 bits are sampled by a PLL clock and then sent to 32 IO_OBUF pins. The same PLL clock (which samples the 32 data bits) is connected to another IO_OBUF.

I would like to align the clock and the 32 data bits to the same flip-flop delay value.

Is there an IP core or an alternative method to create an ODDR that is sampled by the PLL clock and generates a new clock that is aligned with the flip-flop for the 32 data bits?

Thank you!

Fpga Devkit
  • FvM's avatar
    FvM
    1 year ago

    Hi,
    there's probably no advantage by using GPIO. A behavioral or structural description of the output logic will most likely end up in a similar or identical hardware implementation. I mentioned GPIO because you asked.

    Also your existing SDC specification should work.

8 Replies

  • AqidAyman_Altera's avatar
    AqidAyman_Altera
    Icon for Regular Contributor rankRegular Contributor
    1 year ago

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    • ymiler's avatar
      ymiler
      Icon for Contributor rankContributor
      1 year ago

      My device is Stratix 10,

      My Quartus version is Quartus Prime Pro Edition 22.3

      I don't find ALTDDIO IP in this version, maybe there is other IP which relevant to my version / device?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    in Quartus Pro, ODDR and IDDR functions are contained in GPIO Intel IP.

    • ymiler's avatar
      ymiler
      Icon for Contributor rankContributor
      1 year ago

      OK ,

      I have several Q

      1)Currently , my SDC file include definition of the PLL clock and input & output delay to the data output ports

      Should I change the constraints since I add GPIO IP which get the PLL clock as input ?

      2)Should I expect better result with the GPIO IP ?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 year ago

    Hi,
    there's probably no advantage by using GPIO. A behavioral or structural description of the output logic will most likely end up in a similar or identical hardware implementation. I mentioned GPIO because you asked.

    Also your existing SDC specification should work.