Forum Discussion
ymiler
Contributor
ContributorODDR clock
Hi, I need to create a source synchronous connection between two FPGAs. FPGA A needs to transmit 32 data bits with a clock to FPGA B. All 32 bits are sampled by a PLL clock and then sent to 32 IO_...
Hi,
there's probably no advantage by using GPIO. A behavioral or structural description of the output logic will most likely end up in a similar or identical hardware implementation. I mentioned GPIO because you asked.
Also your existing SDC specification should work.
AqidAyman_Altera
Regular Contributor
Regular ContributorHello,
It seems like a Double Data Rate I/O IP. I share you the link to the IP user guide:
Regards,
Aqid
ymilerContributor
ContributorMy device is Stratix 10,
My Quartus version is Quartus Prime Pro Edition 22.3
I don't find ALTDDIO IP in this version, maybe there is other IP which relevant to my version / device?
