Forum Discussion
ymiler
Contributor
ContributorODDR clock
Hi, I need to create a source synchronous connection between two FPGAs. FPGA A needs to transmit 32 data bits with a clock to FPGA B. All 32 bits are sampled by a PLL clock and then sent to 32 IO_...
Hi,
there's probably no advantage by using GPIO. A behavioral or structural description of the output logic will most likely end up in a similar or identical hardware implementation. I mentioned GPIO because you asked.
Also your existing SDC specification should work.
FvM
Super Contributor
Super ContributorHi,
in Quartus Pro, ODDR and IDDR functions are contained in GPIO Intel IP.
ymilerContributor
ContributorOK ,
I have several Q
1)Currently , my SDC file include definition of the PLL clock and input & output delay to the data output ports
Should I change the constraints since I add GPIO IP which get the PLL clock as input ?
2)Should I expect better result with the GPIO IP ?
