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Honored ContributorNEEK Cyclone III edition problem
I am trying to create a simple project like Hello World or counter. I made a design but always getting error like;
Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Pausing target processor: OK Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused Using cable "USB-Blaster [USB-0]", device 1, instance 0x00 Processor is already paused Initializing CPU cache (if present) OK Downloading 02000000 ( 0%) Downloaded 20KB in 0.3s (66.6KB/s) Verifying 02000000 ( 0%) Verify failed between address 0x2000000 and 0x2004E0F Leaving target processor paused I tried to attached my project file but i think it has big size to attach. Could you help me please..17 Replies
Altera_ForumWhat type of memory is at address 0x2000000 in your system?
SDRAM? Usually you get this error when the memory is not correctly working, because of bad clocking, wrong assignments, timing not met.- Altera_Forum
I attached my SOPC design. I tried to be very careful about pin assignments.
Actually 0x200000 is the starting address of SDRAM - Altera_Forum
How much is pll_c2 clock frequency you are using to drive Nios and sdram?
Is your design fully time constrained? Do you get any warning in the TQ reports? Which clock do you use to drive the sdram clk input? Have you tuned relative phase between sdram clock and pll_c2 in order to meet setup and hold requirements? - Altera_Forum
pll_c2 is 133 MHz.
I have 47 warnings as result of the Time Quest Analysis. I fed sdram with pll_c2 on SOPC. İ did not tuned any phase. Here i added warnings of TQ analysis - Altera_Forum
These you posted are not TQ warnings. You must open TQ to get the complete reports about timing analysis.
Anyway I can see in the underlying pane you have 6 "critical warnings": those are probably your real problem. Display them. I suppose they are sort of "timing not met" Running Nios at 133MHz on a CIII device can be very challenging. I don't mean it is impossible, but you must be smart in placing timing contraints and be sure to meet all of them after every recompilation. Moreover I don't think the device on the NEEK board is the fastest speed grade, so this won't help you. I suggest you start testing your design with maximum of 100MHz, which is a rather safe frequency and you should get all things working rather easily. Regarding the phase, usually you need to generate the clock feeding the external sdram clock pin with a small phase lead relative to the system clock of Nios and sdram controller. You make this with an additional pll output. The required phase lead can be derived from post fit analysis of delays of sdram signals and from sdram setup and hold specification. My rule of thumb is that 1ns phase lead is good with a 100MHz clock. Regards Cris - Altera_Forum
thanks for your replies. I am really new on FPGAs so i dont know much about them. İ will try to do what you said but i am not sure that i can make it. Thanks again and i will reply you when i tried what you told.
- Altera_Forum
Hi Cris;
I tried things you said. I changed pll frequency to 66.5 Mhz and delayed for 1 ns but still not works. Do you have any suggestions ? - Altera_Forum
First of all you must identify if your problem is with sdram or elsewhere.
You can try running Nios code from onchip ram, so you exclude sdram timing problems and external connection. I think your fpga has enough onchip ram to fit the 20kB required by your test application. Steps: - add at least 32kb onchip ram with sopc builder - change Nios properties: start and exception vectors must point to onchip ram - generate the system - recompile fpga - change nios syslib properties so that code, stack, data are mapped to onchip ram - rebuild nios application When you are able to run the application with this modified system, you can focus on sdram. You can even use the application itself to perform some tests on sdram reading and writing data. - Altera_Forum
First of all, onchip ram is only 4kB on my kit.
Today,I did something like you said and i was able to run counter example without sdram. - Altera_Forum--- Quote Start --- First of all, onchip ram is only 4kB on my kit. --- Quote End --- Are you sure of this? afaik the CIII NEEK kit comes with a 3C25 device, which has 594kbits of memory: this means 66KBytes available to implement onchip ram. Probably you mean your current[/I][/I] sopc system has 4kB ram: you simply need to use sopc builder to increase the ram size or add another onchip ram component.
